165 lines
8.4 KiB
TableGen
165 lines
8.4 KiB
TableGen
//===--- HexagonIICScalar.td ----------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// These itinerary class descriptions are based on the instruction timing
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// classes as per V62. Curretnly, they are just extracted from
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// HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
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class ScalarItin {
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list<InstrItinData> ScalarItin_list = [
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InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
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InstrItinData<ALU32_2op_tc_2early_SLOT0123,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
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InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
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InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
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InstrItinData<ALU32_3op_tc_2early_SLOT0123,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
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InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
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// ALU64
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InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1]>,
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// CR -> System
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InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
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InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
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InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>], [3, 1, 1]>,
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// Jump (conditional/unconditional/return etc)
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InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1, 1]>,
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InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1, 1]>,
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InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[1, 1, 1, 1]>,
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InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1, 1]>,
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InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1, 1]>,
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InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1, 1]>,
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// JR
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InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>], [2, 1, 1]>,
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InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<1, [SLOT2]>], [3, 1, 1]>,
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// Extender
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InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1,
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[SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1, 1]>,
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// Load
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InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
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[3, 1]>,
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InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
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[3, 1]>,
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InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [4, 1]>,
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InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [3, 1]>,
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// M
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InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1]>,
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InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1]>,
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InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1, 1]>,
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InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[4, 1, 1]>,
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InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[4, 1, 1]>,
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InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1]>,
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// Store
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InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
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[1, 1, 1]>,
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InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
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[1, 1, 1]>,
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InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [3, 1, 1]>,
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InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [3, 1, 1]>,
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InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
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InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
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// S
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InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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// The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60.
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InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[4, 1, 1]>,
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InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1]>,
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InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1]>,
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InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1]>,
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InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1]>,
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// New Value Compare Jump
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InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>],
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[3, 1, 1, 1]>,
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// Mem ops
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InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
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[1, 1, 1, 1]>,
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InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
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[2, 1, 1, 1]>,
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InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
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[1, 1, 1, 1]>,
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InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
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[1, 1, 1, 1]>,
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InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
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[3, 1, 1, 1]>,
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InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
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[1, 1, 1, 1]>,
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// Endloop
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InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>],
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[2]>,
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InstrItinData<MAPPING_tc_1_SLOT0123 ,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
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[1, 1, 1, 1]>,
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// Duplex and Compound
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InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
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InstrItinData<COMPOUND_CJ_ARCHDEPSLOT,
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[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
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InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
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// Misc
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InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
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[1, 1, 1]>,
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InstrItinData<PSEUDOM , [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>];
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}
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