27 lines
1.1 KiB
TableGen
27 lines
1.1 KiB
TableGen
//==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Qualcomm Falkor to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Define the SchedMachineModel and provide basic properties for coarse grained
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// instruction cost model.
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def FalkorModel : SchedMachineModel {
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let IssueWidth = 4; // 4-wide issue for expanded uops.
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let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
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let LoopMicroOpBufferSize = 16;
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let LoadLatency = 3; // Optimistic load latency.
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let MispredictPenalty = 11; // Minimum branch misprediction penalty.
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let CompleteModel = 0;
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}
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