Alex Bradbury 52c27785ce [RISCV] Add some missing expansions for floating-point intrinsics ... A number of intrinsics, such as llvm.sin.f32, would result in a failure to select. This patch adds expansions for the relevant selection DAG nodes, as well as exhaustive testing for all f32 and f64 intrinsics. The codegen for FMA remains a TODO item, pending support for the various RISC-V FMA instruction variants. The llvm.minimum.f32.* and llvm.maximum.* tests are commented-out, pending upstream support for target-independent expansion, as discussed in http://lists.llvm.org/pipermail/llvm-dev/2018-November/127408.html. Differential Revision: https://reviews.llvm.org/D54034 Patch by Luís Marques. llvm-svn: 346034		2018-11-02 19:50:38 +00:00
..
addc-adde-sube-subc.ll	…
align.ll	…
alloca.ll	…
alu8.ll	[RISCV] Eliminate unnecessary masking of promoted shift amounts	2018-10-12 23:18:52 +00:00
alu16.ll	[RISCV] Eliminate unnecessary masking of promoted shift amounts	2018-10-12 23:18:52 +00:00
alu32.ll	…
analyze-branch.ll	…
arith-with-overflow.ll	[RISCV] Add tests for overflow intrinsics	2018-06-19 06:45:47 +00:00
atomic-cmpxchg.ll	[RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by default	2018-10-05 18:25:55 +00:00
atomic-fence.ll	[RISCV] Codegen support for atomic operations on RV32I	2018-06-13 11:58:46 +00:00
atomic-load-store.ll	[RISCV] atomic_store_nn have a different layout to regular store	2018-08-27 07:08:18 +00:00
atomic-rmw.ll	[RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A	2018-09-19 10:54:22 +00:00
bare-select.ll	…
blockaddress.ll	…
branch-relaxation.ll	…
branch.ll	…
bswap-ctlz-cttz-ctpop.ll	…
byval.ll	…
calling-conv-rv32f-ilp32.ll	[RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F	2018-10-04 07:28:49 +00:00
calling-conv-sext-zext.ll	…
calling-conv.ll	…
calls.ll	…
compress-inline-asm.ll	…
compress.ll	…
disable-tail-calls.ll	…
div.ll	…
double-arith.ll	…
double-br-fcmp.ll	…
double-calling-conv.ll	…
double-convert.ll	…
double-fcmp.ll	…
double-imm.ll	…
double-intrinsics.ll	[RISCV] Add some missing expansions for floating-point intrinsics	2018-11-02 19:50:38 +00:00
double-mem.ll	…
double-previous-failure.ll	…
double-select-fcmp.ll	[RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by default	2018-10-05 18:25:55 +00:00
double-stack-spill-restore.ll	…
fixups-diff.ll	[RISCV][MC] Don't fold symbol differences if requiresDiffExpressionRelocations is true	2018-08-16 11:26:37 +00:00
float-arith.ll	…
float-br-fcmp.ll	…
float-convert.ll	…
float-fcmp.ll	…
float-imm.ll	…
float-intrinsics.ll	[RISCV] Add some missing expansions for floating-point intrinsics	2018-11-02 19:50:38 +00:00
float-mem.ll	…
float-select-fcmp.ll	…
fp128.ll	…
frame.ll	…
frameaddr-returnaddr.ll	…
get-setcc-result-type.ll	…
hoist-global-addr-base.ll	[RISCV] Add machine function pass to merge base + offset	2018-06-27 20:51:42 +00:00
i32-icmp.ll	…
imm-cse.ll	…
imm.ll	…
indirectbr.ll	[RISC-V] Fix a test case to not include label names as those aren't	2018-06-21 05:42:05 +00:00
init-array.ll	…
inline-asm.ll	…
interrupt-attr-args-error.ll	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
interrupt-attr-invalid.ll	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
interrupt-attr-nocall.ll	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
interrupt-attr-ret-error.ll	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
interrupt-attr.ll	[RISCV] Add support for _interrupt attribute	2018-07-26 17:49:43 +00:00
jumptable.ll	…
large-stack.ll	…
lit.local.cfg	…
lsr-legaladdimm.ll	…
mem.ll	…
mul.ll	…
musttail-call.ll	…
option-norvc.ll	…
option-rvc.ll	…
rem.ll	…
remat.ll	…
rotl-rotr.ll	…
select-cc.ll	…
sext-zext-trunc.ll	…
shift-masked-shamt.ll	[RISCV] Eliminate unnecessary masking of promoted shift amounts	2018-10-12 23:18:52 +00:00
shifts.ll	…
tail-calls.ll	[RISCV] Fixed test case failure due to r338047	2018-07-31 00:36:28 +00:00
umulo-128-legalisation-lowering.ll	[RISCV] Remove RV64 test lines from umulo-128-legalisation-lowering.ll	2018-10-03 10:59:42 +00:00
vararg.ll	[RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142	2018-10-11 11:11:58 +00:00
wide-mem.ll	…
zext-with-load-is-free.ll	…