1227 lines
42 KiB
C++
1227 lines
42 KiB
C++
//===-- RegisterContextDarwin_arm.cpp ---------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#if defined(__APPLE__)
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#include "RegisterContextDarwin_arm.h"
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// C Includes
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#include <mach/mach_types.h>
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#include <mach/thread_act.h>
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// C++ Includes
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// Other libraries and framework includes
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#include "lldb/Core/DataBufferHeap.h"
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#include "lldb/Core/DataExtractor.h"
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#include "lldb/Core/Log.h"
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#include "lldb/Core/RegisterValue.h"
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#include "lldb/Core/Scalar.h"
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#include "lldb/Host/Endian.h"
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#include "llvm/Support/Compiler.h"
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#include "Plugins/Process/Utility/InstructionUtils.h"
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// Support building against older versions of LLVM, this macro was added
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// recently.
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#ifndef LLVM_EXTENSION
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#define LLVM_EXTENSION
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#endif
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// Project includes
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#include "ARM_GCC_Registers.h"
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#include "ARM_DWARF_Registers.h"
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using namespace lldb;
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using namespace lldb_private;
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enum
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{
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gpr_r0 = 0,
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gpr_r1,
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gpr_r2,
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gpr_r3,
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gpr_r4,
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gpr_r5,
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gpr_r6,
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gpr_r7,
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gpr_r8,
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gpr_r9,
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gpr_r10,
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gpr_r11,
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gpr_r12,
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gpr_r13, gpr_sp = gpr_r13,
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gpr_r14, gpr_lr = gpr_r14,
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gpr_r15, gpr_pc = gpr_r15,
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gpr_cpsr,
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fpu_s0,
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fpu_s1,
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fpu_s2,
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fpu_s3,
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fpu_s4,
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fpu_s5,
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fpu_s6,
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fpu_s7,
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fpu_s8,
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fpu_s9,
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fpu_s10,
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fpu_s11,
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fpu_s12,
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fpu_s13,
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fpu_s14,
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fpu_s15,
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fpu_s16,
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fpu_s17,
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fpu_s18,
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fpu_s19,
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fpu_s20,
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fpu_s21,
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fpu_s22,
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fpu_s23,
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fpu_s24,
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fpu_s25,
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fpu_s26,
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fpu_s27,
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fpu_s28,
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fpu_s29,
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fpu_s30,
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fpu_s31,
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fpu_fpscr,
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exc_exception,
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exc_fsr,
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exc_far,
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dbg_bvr0,
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dbg_bvr1,
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dbg_bvr2,
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dbg_bvr3,
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dbg_bvr4,
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dbg_bvr5,
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dbg_bvr6,
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dbg_bvr7,
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dbg_bvr8,
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dbg_bvr9,
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dbg_bvr10,
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dbg_bvr11,
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dbg_bvr12,
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dbg_bvr13,
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dbg_bvr14,
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dbg_bvr15,
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dbg_bcr0,
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dbg_bcr1,
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dbg_bcr2,
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dbg_bcr3,
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dbg_bcr4,
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dbg_bcr5,
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dbg_bcr6,
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dbg_bcr7,
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dbg_bcr8,
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dbg_bcr9,
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dbg_bcr10,
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dbg_bcr11,
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dbg_bcr12,
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dbg_bcr13,
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dbg_bcr14,
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dbg_bcr15,
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dbg_wvr0,
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dbg_wvr1,
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dbg_wvr2,
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dbg_wvr3,
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dbg_wvr4,
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dbg_wvr5,
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dbg_wvr6,
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dbg_wvr7,
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dbg_wvr8,
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dbg_wvr9,
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dbg_wvr10,
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dbg_wvr11,
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dbg_wvr12,
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dbg_wvr13,
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dbg_wvr14,
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dbg_wvr15,
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dbg_wcr0,
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dbg_wcr1,
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dbg_wcr2,
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dbg_wcr3,
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dbg_wcr4,
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dbg_wcr5,
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dbg_wcr6,
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dbg_wcr7,
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dbg_wcr8,
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dbg_wcr9,
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dbg_wcr10,
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dbg_wcr11,
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dbg_wcr12,
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dbg_wcr13,
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dbg_wcr14,
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dbg_wcr15,
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k_num_registers
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};
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RegisterContextDarwin_arm::RegisterContextDarwin_arm(Thread &thread, uint32_t concrete_frame_idx) :
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RegisterContext(thread, concrete_frame_idx),
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gpr(),
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fpu(),
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exc()
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{
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uint32_t i;
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for (i=0; i<kNumErrors; i++)
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{
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gpr_errs[i] = -1;
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fpu_errs[i] = -1;
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exc_errs[i] = -1;
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}
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}
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RegisterContextDarwin_arm::~RegisterContextDarwin_arm()
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{
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}
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#define GPR_OFFSET(idx) ((idx) * 4)
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#define FPU_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextDarwin_arm::GPR))
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#define EXC_OFFSET(idx) ((idx) * 4 + sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU))
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#define DBG_OFFSET(reg) ((LLVM_EXTENSION offsetof (RegisterContextDarwin_arm::DBG, reg) + sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU) + sizeof (RegisterContextDarwin_arm::EXC)))
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#define DEFINE_DBG(reg, i) #reg, NULL, sizeof(((RegisterContextDarwin_arm::DBG *)NULL)->reg[i]), DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, dbg_##reg##i }, NULL, NULL
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#define REG_CONTEXT_SIZE (sizeof (RegisterContextDarwin_arm::GPR) + sizeof (RegisterContextDarwin_arm::FPU) + sizeof (RegisterContextDarwin_arm::EXC))
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static RegisterInfo g_register_infos[] = {
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// General purpose registers
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// NAME ALT SZ OFFSET ENCODING FORMAT COMPILER DWARF GENERIC GDB LLDB NATIVE VALUE REGS INVALIDATE REGS
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// ====== ======= == ============= ============= ============ =============== =============== ========================= ===================== ============= ========== ===============
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{ "r0", NULL, 4, GPR_OFFSET(0), eEncodingUint, eFormatHex, { gcc_r0, dwarf_r0, LLDB_INVALID_REGNUM, gdb_arm_r0, gpr_r0 }, NULL, NULL},
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{ "r1", NULL, 4, GPR_OFFSET(1), eEncodingUint, eFormatHex, { gcc_r1, dwarf_r1, LLDB_INVALID_REGNUM, gdb_arm_r1, gpr_r1 }, NULL, NULL},
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{ "r2", NULL, 4, GPR_OFFSET(2), eEncodingUint, eFormatHex, { gcc_r2, dwarf_r2, LLDB_INVALID_REGNUM, gdb_arm_r2, gpr_r2 }, NULL, NULL},
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{ "r3", NULL, 4, GPR_OFFSET(3), eEncodingUint, eFormatHex, { gcc_r3, dwarf_r3, LLDB_INVALID_REGNUM, gdb_arm_r3, gpr_r3 }, NULL, NULL},
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{ "r4", NULL, 4, GPR_OFFSET(4), eEncodingUint, eFormatHex, { gcc_r4, dwarf_r4, LLDB_INVALID_REGNUM, gdb_arm_r4, gpr_r4 }, NULL, NULL},
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{ "r5", NULL, 4, GPR_OFFSET(5), eEncodingUint, eFormatHex, { gcc_r5, dwarf_r5, LLDB_INVALID_REGNUM, gdb_arm_r5, gpr_r5 }, NULL, NULL},
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{ "r6", NULL, 4, GPR_OFFSET(6), eEncodingUint, eFormatHex, { gcc_r6, dwarf_r6, LLDB_INVALID_REGNUM, gdb_arm_r6, gpr_r6 }, NULL, NULL},
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{ "r7", NULL, 4, GPR_OFFSET(7), eEncodingUint, eFormatHex, { gcc_r7, dwarf_r7, LLDB_REGNUM_GENERIC_FP, gdb_arm_r7, gpr_r7 }, NULL, NULL},
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{ "r8", NULL, 4, GPR_OFFSET(8), eEncodingUint, eFormatHex, { gcc_r8, dwarf_r8, LLDB_INVALID_REGNUM, gdb_arm_r8, gpr_r8 }, NULL, NULL},
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{ "r9", NULL, 4, GPR_OFFSET(9), eEncodingUint, eFormatHex, { gcc_r9, dwarf_r9, LLDB_INVALID_REGNUM, gdb_arm_r9, gpr_r9 }, NULL, NULL},
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{ "r10", NULL, 4, GPR_OFFSET(10), eEncodingUint, eFormatHex, { gcc_r10, dwarf_r10, LLDB_INVALID_REGNUM, gdb_arm_r10, gpr_r10 }, NULL, NULL},
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{ "r11", NULL, 4, GPR_OFFSET(11), eEncodingUint, eFormatHex, { gcc_r11, dwarf_r11, LLDB_INVALID_REGNUM, gdb_arm_r11, gpr_r11 }, NULL, NULL},
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{ "r12", NULL, 4, GPR_OFFSET(12), eEncodingUint, eFormatHex, { gcc_r12, dwarf_r12, LLDB_INVALID_REGNUM, gdb_arm_r12, gpr_r12 }, NULL, NULL},
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{ "sp", "r13", 4, GPR_OFFSET(13), eEncodingUint, eFormatHex, { gcc_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, gdb_arm_sp, gpr_sp }, NULL, NULL},
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{ "lr", "r14", 4, GPR_OFFSET(14), eEncodingUint, eFormatHex, { gcc_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, gdb_arm_lr, gpr_lr }, NULL, NULL},
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{ "pc", "r15", 4, GPR_OFFSET(15), eEncodingUint, eFormatHex, { gcc_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, gdb_arm_pc, gpr_pc }, NULL, NULL},
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{ "cpsr", "psr", 4, GPR_OFFSET(16), eEncodingUint, eFormatHex, { gcc_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, gdb_arm_cpsr, gpr_cpsr }, NULL, NULL},
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{ "s0", NULL, 4, FPU_OFFSET(0), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, gdb_arm_s0, fpu_s0 }, NULL, NULL},
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{ "s1", NULL, 4, FPU_OFFSET(1), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, gdb_arm_s1, fpu_s1 }, NULL, NULL},
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{ "s2", NULL, 4, FPU_OFFSET(2), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, gdb_arm_s2, fpu_s2 }, NULL, NULL},
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{ "s3", NULL, 4, FPU_OFFSET(3), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, gdb_arm_s3, fpu_s3 }, NULL, NULL},
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{ "s4", NULL, 4, FPU_OFFSET(4), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, gdb_arm_s4, fpu_s4 }, NULL, NULL},
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{ "s5", NULL, 4, FPU_OFFSET(5), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, gdb_arm_s5, fpu_s5 }, NULL, NULL},
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{ "s6", NULL, 4, FPU_OFFSET(6), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, gdb_arm_s6, fpu_s6 }, NULL, NULL},
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{ "s7", NULL, 4, FPU_OFFSET(7), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, gdb_arm_s7, fpu_s7 }, NULL, NULL},
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{ "s8", NULL, 4, FPU_OFFSET(8), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, gdb_arm_s8, fpu_s8 }, NULL, NULL},
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{ "s9", NULL, 4, FPU_OFFSET(9), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, gdb_arm_s9, fpu_s9 }, NULL, NULL},
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{ "s10", NULL, 4, FPU_OFFSET(10), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, gdb_arm_s10, fpu_s10 }, NULL, NULL},
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{ "s11", NULL, 4, FPU_OFFSET(11), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, gdb_arm_s11, fpu_s11 }, NULL, NULL},
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{ "s12", NULL, 4, FPU_OFFSET(12), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, gdb_arm_s12, fpu_s12 }, NULL, NULL},
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{ "s13", NULL, 4, FPU_OFFSET(13), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, gdb_arm_s13, fpu_s13 }, NULL, NULL},
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{ "s14", NULL, 4, FPU_OFFSET(14), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, gdb_arm_s14, fpu_s14 }, NULL, NULL},
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{ "s15", NULL, 4, FPU_OFFSET(15), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, gdb_arm_s15, fpu_s15 }, NULL, NULL},
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{ "s16", NULL, 4, FPU_OFFSET(16), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, gdb_arm_s16, fpu_s16 }, NULL, NULL},
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{ "s17", NULL, 4, FPU_OFFSET(17), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, gdb_arm_s17, fpu_s17 }, NULL, NULL},
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{ "s18", NULL, 4, FPU_OFFSET(18), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, gdb_arm_s18, fpu_s18 }, NULL, NULL},
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{ "s19", NULL, 4, FPU_OFFSET(19), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, gdb_arm_s19, fpu_s19 }, NULL, NULL},
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{ "s20", NULL, 4, FPU_OFFSET(20), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, gdb_arm_s20, fpu_s20 }, NULL, NULL},
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{ "s21", NULL, 4, FPU_OFFSET(21), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, gdb_arm_s21, fpu_s21 }, NULL, NULL},
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{ "s22", NULL, 4, FPU_OFFSET(22), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, gdb_arm_s22, fpu_s22 }, NULL, NULL},
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{ "s23", NULL, 4, FPU_OFFSET(23), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, gdb_arm_s23, fpu_s23 }, NULL, NULL},
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{ "s24", NULL, 4, FPU_OFFSET(24), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, gdb_arm_s24, fpu_s24 }, NULL, NULL},
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{ "s25", NULL, 4, FPU_OFFSET(25), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, gdb_arm_s25, fpu_s25 }, NULL, NULL},
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{ "s26", NULL, 4, FPU_OFFSET(26), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, gdb_arm_s26, fpu_s26 }, NULL, NULL},
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{ "s27", NULL, 4, FPU_OFFSET(27), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, gdb_arm_s27, fpu_s27 }, NULL, NULL},
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{ "s28", NULL, 4, FPU_OFFSET(28), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, gdb_arm_s28, fpu_s28 }, NULL, NULL},
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{ "s29", NULL, 4, FPU_OFFSET(29), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, gdb_arm_s29, fpu_s29 }, NULL, NULL},
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{ "s30", NULL, 4, FPU_OFFSET(30), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, gdb_arm_s30, fpu_s30 }, NULL, NULL},
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{ "s31", NULL, 4, FPU_OFFSET(31), eEncodingIEEE754,eFormatFloat, { LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, gdb_arm_s31, fpu_s31 }, NULL, NULL},
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{ "fpscr", NULL, 4, FPU_OFFSET(32), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, gdb_arm_fpscr, fpu_fpscr }, NULL, NULL},
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{ "exception",NULL, 4, EXC_OFFSET(0), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_exception }, NULL, NULL},
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{ "fsr", NULL, 4, EXC_OFFSET(1), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_fsr }, NULL, NULL},
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{ "far", NULL, 4, EXC_OFFSET(2), eEncodingUint, eFormatHex, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, exc_far }, NULL, NULL},
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{ DEFINE_DBG (bvr, 0) },
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{ DEFINE_DBG (bvr, 1) },
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{ DEFINE_DBG (bvr, 2) },
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{ DEFINE_DBG (bvr, 3) },
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{ DEFINE_DBG (bvr, 4) },
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{ DEFINE_DBG (bvr, 5) },
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{ DEFINE_DBG (bvr, 6) },
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{ DEFINE_DBG (bvr, 7) },
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{ DEFINE_DBG (bvr, 8) },
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{ DEFINE_DBG (bvr, 9) },
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{ DEFINE_DBG (bvr, 10) },
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{ DEFINE_DBG (bvr, 11) },
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{ DEFINE_DBG (bvr, 12) },
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{ DEFINE_DBG (bvr, 13) },
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{ DEFINE_DBG (bvr, 14) },
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{ DEFINE_DBG (bvr, 15) },
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{ DEFINE_DBG (bcr, 0) },
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{ DEFINE_DBG (bcr, 1) },
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{ DEFINE_DBG (bcr, 2) },
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{ DEFINE_DBG (bcr, 3) },
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{ DEFINE_DBG (bcr, 4) },
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{ DEFINE_DBG (bcr, 5) },
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{ DEFINE_DBG (bcr, 6) },
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{ DEFINE_DBG (bcr, 7) },
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{ DEFINE_DBG (bcr, 8) },
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{ DEFINE_DBG (bcr, 9) },
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{ DEFINE_DBG (bcr, 10) },
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{ DEFINE_DBG (bcr, 11) },
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{ DEFINE_DBG (bcr, 12) },
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{ DEFINE_DBG (bcr, 13) },
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{ DEFINE_DBG (bcr, 14) },
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{ DEFINE_DBG (bcr, 15) },
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{ DEFINE_DBG (wvr, 0) },
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{ DEFINE_DBG (wvr, 1) },
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{ DEFINE_DBG (wvr, 2) },
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{ DEFINE_DBG (wvr, 3) },
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{ DEFINE_DBG (wvr, 4) },
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{ DEFINE_DBG (wvr, 5) },
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{ DEFINE_DBG (wvr, 6) },
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{ DEFINE_DBG (wvr, 7) },
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{ DEFINE_DBG (wvr, 8) },
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{ DEFINE_DBG (wvr, 9) },
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{ DEFINE_DBG (wvr, 10) },
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{ DEFINE_DBG (wvr, 11) },
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{ DEFINE_DBG (wvr, 12) },
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{ DEFINE_DBG (wvr, 13) },
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{ DEFINE_DBG (wvr, 14) },
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{ DEFINE_DBG (wvr, 15) },
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{ DEFINE_DBG (wcr, 0) },
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{ DEFINE_DBG (wcr, 1) },
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{ DEFINE_DBG (wcr, 2) },
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{ DEFINE_DBG (wcr, 3) },
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{ DEFINE_DBG (wcr, 4) },
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{ DEFINE_DBG (wcr, 5) },
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{ DEFINE_DBG (wcr, 6) },
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{ DEFINE_DBG (wcr, 7) },
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{ DEFINE_DBG (wcr, 8) },
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{ DEFINE_DBG (wcr, 9) },
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{ DEFINE_DBG (wcr, 10) },
|
|
{ DEFINE_DBG (wcr, 11) },
|
|
{ DEFINE_DBG (wcr, 12) },
|
|
{ DEFINE_DBG (wcr, 13) },
|
|
{ DEFINE_DBG (wcr, 14) },
|
|
{ DEFINE_DBG (wcr, 15) }
|
|
};
|
|
|
|
// General purpose registers
|
|
static uint32_t
|
|
g_gpr_regnums[] =
|
|
{
|
|
gpr_r0,
|
|
gpr_r1,
|
|
gpr_r2,
|
|
gpr_r3,
|
|
gpr_r4,
|
|
gpr_r5,
|
|
gpr_r6,
|
|
gpr_r7,
|
|
gpr_r8,
|
|
gpr_r9,
|
|
gpr_r10,
|
|
gpr_r11,
|
|
gpr_r12,
|
|
gpr_sp,
|
|
gpr_lr,
|
|
gpr_pc,
|
|
gpr_cpsr
|
|
};
|
|
|
|
// Floating point registers
|
|
static uint32_t
|
|
g_fpu_regnums[] =
|
|
{
|
|
fpu_s0,
|
|
fpu_s1,
|
|
fpu_s2,
|
|
fpu_s3,
|
|
fpu_s4,
|
|
fpu_s5,
|
|
fpu_s6,
|
|
fpu_s7,
|
|
fpu_s8,
|
|
fpu_s9,
|
|
fpu_s10,
|
|
fpu_s11,
|
|
fpu_s12,
|
|
fpu_s13,
|
|
fpu_s14,
|
|
fpu_s15,
|
|
fpu_s16,
|
|
fpu_s17,
|
|
fpu_s18,
|
|
fpu_s19,
|
|
fpu_s20,
|
|
fpu_s21,
|
|
fpu_s22,
|
|
fpu_s23,
|
|
fpu_s24,
|
|
fpu_s25,
|
|
fpu_s26,
|
|
fpu_s27,
|
|
fpu_s28,
|
|
fpu_s29,
|
|
fpu_s30,
|
|
fpu_s31,
|
|
fpu_fpscr,
|
|
};
|
|
|
|
// Exception registers
|
|
|
|
static uint32_t
|
|
g_exc_regnums[] =
|
|
{
|
|
exc_exception,
|
|
exc_fsr,
|
|
exc_far,
|
|
};
|
|
|
|
static size_t k_num_register_infos = (sizeof(g_register_infos)/sizeof(RegisterInfo));
|
|
|
|
void
|
|
RegisterContextDarwin_arm::InvalidateAllRegisters ()
|
|
{
|
|
InvalidateAllRegisterStates();
|
|
}
|
|
|
|
|
|
size_t
|
|
RegisterContextDarwin_arm::GetRegisterCount ()
|
|
{
|
|
assert(k_num_register_infos == k_num_registers);
|
|
return k_num_registers;
|
|
}
|
|
|
|
const RegisterInfo *
|
|
RegisterContextDarwin_arm::GetRegisterInfoAtIndex (size_t reg)
|
|
{
|
|
assert(k_num_register_infos == k_num_registers);
|
|
if (reg < k_num_registers)
|
|
return &g_register_infos[reg];
|
|
return NULL;
|
|
}
|
|
|
|
size_t
|
|
RegisterContextDarwin_arm::GetRegisterInfosCount ()
|
|
{
|
|
return k_num_register_infos;
|
|
}
|
|
|
|
const RegisterInfo *
|
|
RegisterContextDarwin_arm::GetRegisterInfos ()
|
|
{
|
|
return g_register_infos;
|
|
}
|
|
|
|
|
|
// Number of registers in each register set
|
|
const size_t k_num_gpr_registers = sizeof(g_gpr_regnums) / sizeof(uint32_t);
|
|
const size_t k_num_fpu_registers = sizeof(g_fpu_regnums) / sizeof(uint32_t);
|
|
const size_t k_num_exc_registers = sizeof(g_exc_regnums) / sizeof(uint32_t);
|
|
|
|
//----------------------------------------------------------------------
|
|
// Register set definitions. The first definitions at register set index
|
|
// of zero is for all registers, followed by other registers sets. The
|
|
// register information for the all register set need not be filled in.
|
|
//----------------------------------------------------------------------
|
|
static const RegisterSet g_reg_sets[] =
|
|
{
|
|
{ "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums, },
|
|
{ "Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums },
|
|
{ "Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums }
|
|
};
|
|
|
|
const size_t k_num_regsets = sizeof(g_reg_sets) / sizeof(RegisterSet);
|
|
|
|
|
|
size_t
|
|
RegisterContextDarwin_arm::GetRegisterSetCount ()
|
|
{
|
|
return k_num_regsets;
|
|
}
|
|
|
|
const RegisterSet *
|
|
RegisterContextDarwin_arm::GetRegisterSet (size_t reg_set)
|
|
{
|
|
if (reg_set < k_num_regsets)
|
|
return &g_reg_sets[reg_set];
|
|
return NULL;
|
|
}
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
// Register information defintions for 32 bit i386.
|
|
//----------------------------------------------------------------------
|
|
int
|
|
RegisterContextDarwin_arm::GetSetForNativeRegNum (int reg)
|
|
{
|
|
if (reg < fpu_s0)
|
|
return GPRRegSet;
|
|
else if (reg < exc_exception)
|
|
return FPURegSet;
|
|
else if (reg < k_num_registers)
|
|
return EXCRegSet;
|
|
return -1;
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::ReadGPR (bool force)
|
|
{
|
|
int set = GPRRegSet;
|
|
if (force || !RegisterSetIsCached(set))
|
|
{
|
|
SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
|
|
}
|
|
return GetError(GPRRegSet, Read);
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::ReadFPU (bool force)
|
|
{
|
|
int set = FPURegSet;
|
|
if (force || !RegisterSetIsCached(set))
|
|
{
|
|
SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
|
|
}
|
|
return GetError(FPURegSet, Read);
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::ReadEXC (bool force)
|
|
{
|
|
int set = EXCRegSet;
|
|
if (force || !RegisterSetIsCached(set))
|
|
{
|
|
SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
|
|
}
|
|
return GetError(EXCRegSet, Read);
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::ReadDBG (bool force)
|
|
{
|
|
int set = DBGRegSet;
|
|
if (force || !RegisterSetIsCached(set))
|
|
{
|
|
SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
|
|
}
|
|
return GetError(DBGRegSet, Read);
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::WriteGPR ()
|
|
{
|
|
int set = GPRRegSet;
|
|
if (!RegisterSetIsCached(set))
|
|
{
|
|
SetError (set, Write, -1);
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
SetError (set, Write, DoWriteGPR(GetThreadID(), set, gpr));
|
|
SetError (set, Read, -1);
|
|
return GetError(GPRRegSet, Write);
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::WriteFPU ()
|
|
{
|
|
int set = FPURegSet;
|
|
if (!RegisterSetIsCached(set))
|
|
{
|
|
SetError (set, Write, -1);
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
SetError (set, Write, DoWriteFPU(GetThreadID(), set, fpu));
|
|
SetError (set, Read, -1);
|
|
return GetError(FPURegSet, Write);
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::WriteEXC ()
|
|
{
|
|
int set = EXCRegSet;
|
|
if (!RegisterSetIsCached(set))
|
|
{
|
|
SetError (set, Write, -1);
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
SetError (set, Write, DoWriteEXC(GetThreadID(), set, exc));
|
|
SetError (set, Read, -1);
|
|
return GetError(EXCRegSet, Write);
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::WriteDBG ()
|
|
{
|
|
int set = DBGRegSet;
|
|
if (!RegisterSetIsCached(set))
|
|
{
|
|
SetError (set, Write, -1);
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
SetError (set, Write, DoWriteDBG(GetThreadID(), set, dbg));
|
|
SetError (set, Read, -1);
|
|
return GetError(DBGRegSet, Write);
|
|
}
|
|
|
|
|
|
int
|
|
RegisterContextDarwin_arm::ReadRegisterSet (uint32_t set, bool force)
|
|
{
|
|
switch (set)
|
|
{
|
|
case GPRRegSet: return ReadGPR(force);
|
|
case FPURegSet: return ReadFPU(force);
|
|
case EXCRegSet: return ReadEXC(force);
|
|
case DBGRegSet: return ReadDBG(force);
|
|
default: break;
|
|
}
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
|
|
int
|
|
RegisterContextDarwin_arm::WriteRegisterSet (uint32_t set)
|
|
{
|
|
// Make sure we have a valid context to set.
|
|
if (RegisterSetIsCached(set))
|
|
{
|
|
switch (set)
|
|
{
|
|
case GPRRegSet: return WriteGPR();
|
|
case FPURegSet: return WriteFPU();
|
|
case EXCRegSet: return WriteEXC();
|
|
case DBGRegSet: return WriteDBG();
|
|
default: break;
|
|
}
|
|
}
|
|
return KERN_INVALID_ARGUMENT;
|
|
}
|
|
|
|
void
|
|
RegisterContextDarwin_arm::LogDBGRegisters (Log *log, const DBG& dbg)
|
|
{
|
|
if (log)
|
|
{
|
|
for (uint32_t i=0; i<16; i++)
|
|
log->Printf("BVR%-2u/BCR%-2u = { 0x%8.8x, 0x%8.8x } WVR%-2u/WCR%-2u = { 0x%8.8x, 0x%8.8x }",
|
|
i, i, dbg.bvr[i], dbg.bcr[i],
|
|
i, i, dbg.wvr[i], dbg.wcr[i]);
|
|
}
|
|
}
|
|
|
|
|
|
bool
|
|
RegisterContextDarwin_arm::ReadRegister (const RegisterInfo *reg_info, RegisterValue &value)
|
|
{
|
|
const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
|
|
int set = RegisterContextDarwin_arm::GetSetForNativeRegNum (reg);
|
|
|
|
if (set == -1)
|
|
return false;
|
|
|
|
if (ReadRegisterSet(set, false) != KERN_SUCCESS)
|
|
return false;
|
|
|
|
switch (reg)
|
|
{
|
|
case gpr_r0:
|
|
case gpr_r1:
|
|
case gpr_r2:
|
|
case gpr_r3:
|
|
case gpr_r4:
|
|
case gpr_r5:
|
|
case gpr_r6:
|
|
case gpr_r7:
|
|
case gpr_r8:
|
|
case gpr_r9:
|
|
case gpr_r10:
|
|
case gpr_r11:
|
|
case gpr_r12:
|
|
case gpr_sp:
|
|
case gpr_lr:
|
|
case gpr_pc:
|
|
case gpr_cpsr:
|
|
value.SetUInt32 (gpr.r[reg - gpr_r0]);
|
|
break;
|
|
|
|
case fpu_s0:
|
|
case fpu_s1:
|
|
case fpu_s2:
|
|
case fpu_s3:
|
|
case fpu_s4:
|
|
case fpu_s5:
|
|
case fpu_s6:
|
|
case fpu_s7:
|
|
case fpu_s8:
|
|
case fpu_s9:
|
|
case fpu_s10:
|
|
case fpu_s11:
|
|
case fpu_s12:
|
|
case fpu_s13:
|
|
case fpu_s14:
|
|
case fpu_s15:
|
|
case fpu_s16:
|
|
case fpu_s17:
|
|
case fpu_s18:
|
|
case fpu_s19:
|
|
case fpu_s20:
|
|
case fpu_s21:
|
|
case fpu_s22:
|
|
case fpu_s23:
|
|
case fpu_s24:
|
|
case fpu_s25:
|
|
case fpu_s26:
|
|
case fpu_s27:
|
|
case fpu_s28:
|
|
case fpu_s29:
|
|
case fpu_s30:
|
|
case fpu_s31:
|
|
value.SetUInt32 (fpu.floats.s[reg], RegisterValue::eTypeFloat);
|
|
break;
|
|
|
|
case fpu_fpscr:
|
|
value.SetUInt32 (fpu.fpscr);
|
|
break;
|
|
|
|
case exc_exception:
|
|
value.SetUInt32 (exc.exception);
|
|
break;
|
|
case exc_fsr:
|
|
value.SetUInt32 (exc.fsr);
|
|
break;
|
|
case exc_far:
|
|
value.SetUInt32 (exc.far);
|
|
break;
|
|
|
|
default:
|
|
value.SetValueToInvalid();
|
|
return false;
|
|
|
|
}
|
|
return true;
|
|
}
|
|
|
|
|
|
bool
|
|
RegisterContextDarwin_arm::WriteRegister (const RegisterInfo *reg_info,
|
|
const RegisterValue &value)
|
|
{
|
|
const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
|
|
int set = GetSetForNativeRegNum (reg);
|
|
|
|
if (set == -1)
|
|
return false;
|
|
|
|
if (ReadRegisterSet(set, false) != KERN_SUCCESS)
|
|
return false;
|
|
|
|
switch (reg)
|
|
{
|
|
case gpr_r0:
|
|
case gpr_r1:
|
|
case gpr_r2:
|
|
case gpr_r3:
|
|
case gpr_r4:
|
|
case gpr_r5:
|
|
case gpr_r6:
|
|
case gpr_r7:
|
|
case gpr_r8:
|
|
case gpr_r9:
|
|
case gpr_r10:
|
|
case gpr_r11:
|
|
case gpr_r12:
|
|
case gpr_sp:
|
|
case gpr_lr:
|
|
case gpr_pc:
|
|
case gpr_cpsr:
|
|
gpr.r[reg - gpr_r0] = value.GetAsUInt32();
|
|
break;
|
|
|
|
case fpu_s0:
|
|
case fpu_s1:
|
|
case fpu_s2:
|
|
case fpu_s3:
|
|
case fpu_s4:
|
|
case fpu_s5:
|
|
case fpu_s6:
|
|
case fpu_s7:
|
|
case fpu_s8:
|
|
case fpu_s9:
|
|
case fpu_s10:
|
|
case fpu_s11:
|
|
case fpu_s12:
|
|
case fpu_s13:
|
|
case fpu_s14:
|
|
case fpu_s15:
|
|
case fpu_s16:
|
|
case fpu_s17:
|
|
case fpu_s18:
|
|
case fpu_s19:
|
|
case fpu_s20:
|
|
case fpu_s21:
|
|
case fpu_s22:
|
|
case fpu_s23:
|
|
case fpu_s24:
|
|
case fpu_s25:
|
|
case fpu_s26:
|
|
case fpu_s27:
|
|
case fpu_s28:
|
|
case fpu_s29:
|
|
case fpu_s30:
|
|
case fpu_s31:
|
|
fpu.floats.s[reg] = value.GetAsUInt32();
|
|
break;
|
|
|
|
case fpu_fpscr:
|
|
fpu.fpscr = value.GetAsUInt32();
|
|
break;
|
|
|
|
case exc_exception:
|
|
exc.exception = value.GetAsUInt32();
|
|
break;
|
|
case exc_fsr:
|
|
exc.fsr = value.GetAsUInt32();
|
|
break;
|
|
case exc_far:
|
|
exc.far = value.GetAsUInt32();
|
|
break;
|
|
|
|
default:
|
|
return false;
|
|
|
|
}
|
|
return WriteRegisterSet(set) == KERN_SUCCESS;
|
|
}
|
|
|
|
bool
|
|
RegisterContextDarwin_arm::ReadAllRegisterValues (lldb::DataBufferSP &data_sp)
|
|
{
|
|
data_sp.reset (new DataBufferHeap (REG_CONTEXT_SIZE, 0));
|
|
if (data_sp &&
|
|
ReadGPR (false) == KERN_SUCCESS &&
|
|
ReadFPU (false) == KERN_SUCCESS &&
|
|
ReadEXC (false) == KERN_SUCCESS)
|
|
{
|
|
uint8_t *dst = data_sp->GetBytes();
|
|
::memcpy (dst, &gpr, sizeof(gpr));
|
|
dst += sizeof(gpr);
|
|
|
|
::memcpy (dst, &fpu, sizeof(fpu));
|
|
dst += sizeof(gpr);
|
|
|
|
::memcpy (dst, &exc, sizeof(exc));
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool
|
|
RegisterContextDarwin_arm::WriteAllRegisterValues (const lldb::DataBufferSP &data_sp)
|
|
{
|
|
if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE)
|
|
{
|
|
const uint8_t *src = data_sp->GetBytes();
|
|
::memcpy (&gpr, src, sizeof(gpr));
|
|
src += sizeof(gpr);
|
|
|
|
::memcpy (&fpu, src, sizeof(fpu));
|
|
src += sizeof(gpr);
|
|
|
|
::memcpy (&exc, src, sizeof(exc));
|
|
uint32_t success_count = 0;
|
|
if (WriteGPR() == KERN_SUCCESS)
|
|
++success_count;
|
|
if (WriteFPU() == KERN_SUCCESS)
|
|
++success_count;
|
|
if (WriteEXC() == KERN_SUCCESS)
|
|
++success_count;
|
|
return success_count == 3;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
uint32_t
|
|
RegisterContextDarwin_arm::ConvertRegisterKindToRegisterNumber (uint32_t kind, uint32_t reg)
|
|
{
|
|
if (kind == eRegisterKindGeneric)
|
|
{
|
|
switch (reg)
|
|
{
|
|
case LLDB_REGNUM_GENERIC_PC: return gpr_pc;
|
|
case LLDB_REGNUM_GENERIC_SP: return gpr_sp;
|
|
case LLDB_REGNUM_GENERIC_FP: return gpr_r7;
|
|
case LLDB_REGNUM_GENERIC_RA: return gpr_lr;
|
|
case LLDB_REGNUM_GENERIC_FLAGS: return gpr_cpsr;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
else if (kind == eRegisterKindDWARF)
|
|
{
|
|
switch (reg)
|
|
{
|
|
case dwarf_r0: return gpr_r0;
|
|
case dwarf_r1: return gpr_r1;
|
|
case dwarf_r2: return gpr_r2;
|
|
case dwarf_r3: return gpr_r3;
|
|
case dwarf_r4: return gpr_r4;
|
|
case dwarf_r5: return gpr_r5;
|
|
case dwarf_r6: return gpr_r6;
|
|
case dwarf_r7: return gpr_r7;
|
|
case dwarf_r8: return gpr_r8;
|
|
case dwarf_r9: return gpr_r9;
|
|
case dwarf_r10: return gpr_r10;
|
|
case dwarf_r11: return gpr_r11;
|
|
case dwarf_r12: return gpr_r12;
|
|
case dwarf_sp: return gpr_sp;
|
|
case dwarf_lr: return gpr_lr;
|
|
case dwarf_pc: return gpr_pc;
|
|
case dwarf_spsr: return gpr_cpsr;
|
|
|
|
case dwarf_s0: return fpu_s0;
|
|
case dwarf_s1: return fpu_s1;
|
|
case dwarf_s2: return fpu_s2;
|
|
case dwarf_s3: return fpu_s3;
|
|
case dwarf_s4: return fpu_s4;
|
|
case dwarf_s5: return fpu_s5;
|
|
case dwarf_s6: return fpu_s6;
|
|
case dwarf_s7: return fpu_s7;
|
|
case dwarf_s8: return fpu_s8;
|
|
case dwarf_s9: return fpu_s9;
|
|
case dwarf_s10: return fpu_s10;
|
|
case dwarf_s11: return fpu_s11;
|
|
case dwarf_s12: return fpu_s12;
|
|
case dwarf_s13: return fpu_s13;
|
|
case dwarf_s14: return fpu_s14;
|
|
case dwarf_s15: return fpu_s15;
|
|
case dwarf_s16: return fpu_s16;
|
|
case dwarf_s17: return fpu_s17;
|
|
case dwarf_s18: return fpu_s18;
|
|
case dwarf_s19: return fpu_s19;
|
|
case dwarf_s20: return fpu_s20;
|
|
case dwarf_s21: return fpu_s21;
|
|
case dwarf_s22: return fpu_s22;
|
|
case dwarf_s23: return fpu_s23;
|
|
case dwarf_s24: return fpu_s24;
|
|
case dwarf_s25: return fpu_s25;
|
|
case dwarf_s26: return fpu_s26;
|
|
case dwarf_s27: return fpu_s27;
|
|
case dwarf_s28: return fpu_s28;
|
|
case dwarf_s29: return fpu_s29;
|
|
case dwarf_s30: return fpu_s30;
|
|
case dwarf_s31: return fpu_s31;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
else if (kind == eRegisterKindGCC)
|
|
{
|
|
switch (reg)
|
|
{
|
|
case gcc_r0: return gpr_r0;
|
|
case gcc_r1: return gpr_r1;
|
|
case gcc_r2: return gpr_r2;
|
|
case gcc_r3: return gpr_r3;
|
|
case gcc_r4: return gpr_r4;
|
|
case gcc_r5: return gpr_r5;
|
|
case gcc_r6: return gpr_r6;
|
|
case gcc_r7: return gpr_r7;
|
|
case gcc_r8: return gpr_r8;
|
|
case gcc_r9: return gpr_r9;
|
|
case gcc_r10: return gpr_r10;
|
|
case gcc_r11: return gpr_r11;
|
|
case gcc_r12: return gpr_r12;
|
|
case gcc_sp: return gpr_sp;
|
|
case gcc_lr: return gpr_lr;
|
|
case gcc_pc: return gpr_pc;
|
|
case gcc_cpsr: return gpr_cpsr;
|
|
}
|
|
}
|
|
else if (kind == eRegisterKindLLDB)
|
|
{
|
|
return reg;
|
|
}
|
|
return LLDB_INVALID_REGNUM;
|
|
}
|
|
|
|
|
|
uint32_t
|
|
RegisterContextDarwin_arm::NumSupportedHardwareBreakpoints ()
|
|
{
|
|
#if defined (__arm__)
|
|
// Set the init value to something that will let us know that we need to
|
|
// autodetect how many breakpoints are supported dynamically...
|
|
static uint32_t g_num_supported_hw_breakpoints = UINT32_MAX;
|
|
if (g_num_supported_hw_breakpoints == UINT32_MAX)
|
|
{
|
|
// Set this to zero in case we can't tell if there are any HW breakpoints
|
|
g_num_supported_hw_breakpoints = 0;
|
|
|
|
uint32_t register_DBGDIDR;
|
|
|
|
asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR));
|
|
g_num_supported_hw_breakpoints = Bits32 (register_DBGDIDR, 27, 24);
|
|
// Zero is reserved for the BRP count, so don't increment it if it is zero
|
|
if (g_num_supported_hw_breakpoints > 0)
|
|
g_num_supported_hw_breakpoints++;
|
|
// if (log) log->Printf ("DBGDIDR=0x%8.8x (number BRP pairs = %u)", register_DBGDIDR, g_num_supported_hw_breakpoints);
|
|
|
|
}
|
|
return g_num_supported_hw_breakpoints;
|
|
#else
|
|
// TODO: figure out remote case here!
|
|
return 6;
|
|
#endif
|
|
}
|
|
|
|
uint32_t
|
|
RegisterContextDarwin_arm::SetHardwareBreakpoint (lldb::addr_t addr, size_t size)
|
|
{
|
|
// Make sure our address isn't bogus
|
|
if (addr & 1)
|
|
return LLDB_INVALID_INDEX32;
|
|
|
|
int kret = ReadDBG (false);
|
|
|
|
if (kret == KERN_SUCCESS)
|
|
{
|
|
const uint32_t num_hw_breakpoints = NumSupportedHardwareBreakpoints();
|
|
uint32_t i;
|
|
for (i=0; i<num_hw_breakpoints; ++i)
|
|
{
|
|
if ((dbg.bcr[i] & BCR_ENABLE) == 0)
|
|
break; // We found an available hw breakpoint slot (in i)
|
|
}
|
|
|
|
// See if we found an available hw breakpoint slot above
|
|
if (i < num_hw_breakpoints)
|
|
{
|
|
// Make sure bits 1:0 are clear in our address
|
|
dbg.bvr[i] = addr & ~((lldb::addr_t)3);
|
|
|
|
if (size == 2 || addr & 2)
|
|
{
|
|
uint32_t byte_addr_select = (addr & 2) ? BAS_IMVA_2_3 : BAS_IMVA_0_1;
|
|
|
|
// We have a thumb breakpoint
|
|
// We have an ARM breakpoint
|
|
dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
|
|
byte_addr_select | // Set the correct byte address select so we only trigger on the correct opcode
|
|
S_USER | // Which modes should this breakpoint stop in?
|
|
BCR_ENABLE; // Enable this hardware breakpoint
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (Thumb)",
|
|
// addr,
|
|
// size,
|
|
// i,
|
|
// i,
|
|
// dbg.bvr[i],
|
|
// dbg.bcr[i]);
|
|
}
|
|
else if (size == 4)
|
|
{
|
|
// We have an ARM breakpoint
|
|
dbg.bcr[i] = BCR_M_IMVA_MATCH | // Stop on address mismatch
|
|
BAS_IMVA_ALL | // Stop on any of the four bytes following the IMVA
|
|
S_USER | // Which modes should this breakpoint stop in?
|
|
BCR_ENABLE; // Enable this hardware breakpoint
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint( addr = %8.8p, size = %u ) - BVR%u/BCR%u = 0x%8.8x / 0x%8.8x (ARM)",
|
|
// addr,
|
|
// size,
|
|
// i,
|
|
// i,
|
|
// dbg.bvr[i],
|
|
// dbg.bcr[i]);
|
|
}
|
|
|
|
kret = WriteDBG();
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint() WriteDBG() => 0x%8.8x.", kret);
|
|
|
|
if (kret == KERN_SUCCESS)
|
|
return i;
|
|
}
|
|
// else
|
|
// {
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareBreakpoint(addr = %8.8p, size = %u) => all hardware breakpoint resources are being used.", addr, size);
|
|
// }
|
|
}
|
|
|
|
return LLDB_INVALID_INDEX32;
|
|
}
|
|
|
|
bool
|
|
RegisterContextDarwin_arm::ClearHardwareBreakpoint (uint32_t hw_index)
|
|
{
|
|
int kret = ReadDBG (false);
|
|
|
|
const uint32_t num_hw_points = NumSupportedHardwareBreakpoints();
|
|
if (kret == KERN_SUCCESS)
|
|
{
|
|
if (hw_index < num_hw_points)
|
|
{
|
|
dbg.bcr[hw_index] = 0;
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::SetHardwareBreakpoint( %u ) - BVR%u = 0x%8.8x BCR%u = 0x%8.8x",
|
|
// hw_index,
|
|
// hw_index,
|
|
// dbg.bvr[hw_index],
|
|
// hw_index,
|
|
// dbg.bcr[hw_index]);
|
|
|
|
kret = WriteDBG();
|
|
|
|
if (kret == KERN_SUCCESS)
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
uint32_t
|
|
RegisterContextDarwin_arm::NumSupportedHardwareWatchpoints ()
|
|
{
|
|
#if defined (__arm__)
|
|
// Set the init value to something that will let us know that we need to
|
|
// autodetect how many watchpoints are supported dynamically...
|
|
static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
|
|
if (g_num_supported_hw_watchpoints == UINT32_MAX)
|
|
{
|
|
// Set this to zero in case we can't tell if there are any HW breakpoints
|
|
g_num_supported_hw_watchpoints = 0;
|
|
|
|
uint32_t register_DBGDIDR;
|
|
asm("mrc p14, 0, %0, c0, c0, 0" : "=r" (register_DBGDIDR));
|
|
g_num_supported_hw_watchpoints = Bits32 (register_DBGDIDR, 31, 28) + 1;
|
|
// if (log) log->Printf ("DBGDIDR=0x%8.8x (number WRP pairs = %u)", register_DBGDIDR, g_num_supported_hw_watchpoints);
|
|
}
|
|
return g_num_supported_hw_watchpoints;
|
|
#else
|
|
// TODO: figure out remote case here!
|
|
return 2;
|
|
#endif
|
|
}
|
|
|
|
|
|
uint32_t
|
|
RegisterContextDarwin_arm::SetHardwareWatchpoint (lldb::addr_t addr, size_t size, bool read, bool write)
|
|
{
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(addr = %8.8p, size = %u, read = %u, write = %u)", addr, size, read, write);
|
|
|
|
const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
|
|
|
|
// Can't watch zero bytes
|
|
if (size == 0)
|
|
return LLDB_INVALID_INDEX32;
|
|
|
|
// We must watch for either read or write
|
|
if (read == false && write == false)
|
|
return LLDB_INVALID_INDEX32;
|
|
|
|
// Can't watch more than 4 bytes per WVR/WCR pair
|
|
if (size > 4)
|
|
return LLDB_INVALID_INDEX32;
|
|
|
|
// We can only watch up to four bytes that follow a 4 byte aligned address
|
|
// per watchpoint register pair. Since we have at most so we can only watch
|
|
// until the next 4 byte boundary and we need to make sure we can properly
|
|
// encode this.
|
|
uint32_t addr_word_offset = addr % 4;
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - addr_word_offset = 0x%8.8x", addr_word_offset);
|
|
|
|
uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() - byte_mask = 0x%8.8x", byte_mask);
|
|
if (byte_mask > 0xfu)
|
|
return LLDB_INVALID_INDEX32;
|
|
|
|
// Read the debug state
|
|
int kret = ReadDBG (false);
|
|
|
|
if (kret == KERN_SUCCESS)
|
|
{
|
|
// Check to make sure we have the needed hardware support
|
|
uint32_t i = 0;
|
|
|
|
for (i=0; i<num_hw_watchpoints; ++i)
|
|
{
|
|
if ((dbg.wcr[i] & WCR_ENABLE) == 0)
|
|
break; // We found an available hw breakpoint slot (in i)
|
|
}
|
|
|
|
// See if we found an available hw breakpoint slot above
|
|
if (i < num_hw_watchpoints)
|
|
{
|
|
// Make the byte_mask into a valid Byte Address Select mask
|
|
uint32_t byte_address_select = byte_mask << 5;
|
|
// Make sure bits 1:0 are clear in our address
|
|
dbg.wvr[i] = addr & ~((lldb::addr_t)3);
|
|
dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA that we will watch
|
|
S_USER | // Stop only in user mode
|
|
(read ? WCR_LOAD : 0) | // Stop on read access?
|
|
(write ? WCR_STORE : 0) | // Stop on write access?
|
|
WCR_ENABLE; // Enable this watchpoint;
|
|
|
|
kret = WriteDBG();
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint() WriteDBG() => 0x%8.8x.", kret);
|
|
|
|
if (kret == KERN_SUCCESS)
|
|
return i;
|
|
}
|
|
else
|
|
{
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::EnableHardwareWatchpoint(): All hardware resources (%u) are in use.", num_hw_watchpoints);
|
|
}
|
|
}
|
|
return LLDB_INVALID_INDEX32;
|
|
}
|
|
|
|
bool
|
|
RegisterContextDarwin_arm::ClearHardwareWatchpoint (uint32_t hw_index)
|
|
{
|
|
int kret = ReadDBG (false);
|
|
|
|
const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
|
|
if (kret == KERN_SUCCESS)
|
|
{
|
|
if (hw_index < num_hw_points)
|
|
{
|
|
dbg.wcr[hw_index] = 0;
|
|
// if (log) log->Printf ("RegisterContextDarwin_arm::ClearHardwareWatchpoint( %u ) - WVR%u = 0x%8.8x WCR%u = 0x%8.8x",
|
|
// hw_index,
|
|
// hw_index,
|
|
// dbg.wvr[hw_index],
|
|
// hw_index,
|
|
// dbg.wcr[hw_index]);
|
|
|
|
kret = WriteDBG();
|
|
|
|
if (kret == KERN_SUCCESS)
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
#endif
|