926 lines
18 KiB
C++
926 lines
18 KiB
C++
//===-- ARM_DWARF_Registers.cpp ---------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM_DWARF_Registers.h"
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#include <string.h>
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#include <string.h>
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using namespace lldb;
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using namespace lldb_private;
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const char *GetARMDWARFRegisterName(unsigned reg_num) {
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switch (reg_num) {
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case dwarf_r0:
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return "r0";
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case dwarf_r1:
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return "r1";
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case dwarf_r2:
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return "r2";
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case dwarf_r3:
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return "r3";
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case dwarf_r4:
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return "r4";
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case dwarf_r5:
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return "r5";
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case dwarf_r6:
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return "r6";
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case dwarf_r7:
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return "r7";
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case dwarf_r8:
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return "r8";
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case dwarf_r9:
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return "r9";
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case dwarf_r10:
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return "r10";
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case dwarf_r11:
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return "r11";
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case dwarf_r12:
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return "r12";
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case dwarf_sp:
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return "sp";
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case dwarf_lr:
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return "lr";
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case dwarf_pc:
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return "pc";
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case dwarf_cpsr:
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return "cpsr";
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case dwarf_s0:
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return "s0";
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case dwarf_s1:
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return "s1";
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case dwarf_s2:
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return "s2";
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case dwarf_s3:
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return "s3";
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case dwarf_s4:
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return "s4";
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case dwarf_s5:
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return "s5";
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case dwarf_s6:
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return "s6";
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case dwarf_s7:
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return "s7";
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case dwarf_s8:
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return "s8";
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case dwarf_s9:
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return "s9";
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case dwarf_s10:
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return "s10";
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case dwarf_s11:
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return "s11";
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case dwarf_s12:
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return "s12";
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case dwarf_s13:
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return "s13";
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case dwarf_s14:
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return "s14";
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case dwarf_s15:
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return "s15";
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case dwarf_s16:
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return "s16";
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case dwarf_s17:
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return "s17";
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case dwarf_s18:
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return "s18";
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case dwarf_s19:
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return "s19";
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case dwarf_s20:
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return "s20";
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case dwarf_s21:
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return "s21";
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case dwarf_s22:
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return "s22";
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case dwarf_s23:
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return "s23";
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case dwarf_s24:
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return "s24";
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case dwarf_s25:
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return "s25";
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case dwarf_s26:
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return "s26";
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case dwarf_s27:
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return "s27";
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case dwarf_s28:
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return "s28";
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case dwarf_s29:
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return "s29";
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case dwarf_s30:
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return "s30";
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case dwarf_s31:
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return "s31";
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// FPA Registers 0-7
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case dwarf_f0:
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return "f0";
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case dwarf_f1:
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return "f1";
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case dwarf_f2:
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return "f2";
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case dwarf_f3:
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return "f3";
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case dwarf_f4:
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return "f4";
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case dwarf_f5:
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return "f5";
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case dwarf_f6:
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return "f6";
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case dwarf_f7:
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return "f7";
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// Intel wireless MMX general purpose registers 0 - 7
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// XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
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case dwarf_wCGR0:
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return "wCGR0/ACC0";
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case dwarf_wCGR1:
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return "wCGR1/ACC1";
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case dwarf_wCGR2:
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return "wCGR2/ACC2";
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case dwarf_wCGR3:
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return "wCGR3/ACC3";
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case dwarf_wCGR4:
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return "wCGR4/ACC4";
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case dwarf_wCGR5:
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return "wCGR5/ACC5";
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case dwarf_wCGR6:
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return "wCGR6/ACC6";
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case dwarf_wCGR7:
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return "wCGR7/ACC7";
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// Intel wireless MMX data registers 0 - 15
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case dwarf_wR0:
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return "wR0";
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case dwarf_wR1:
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return "wR1";
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case dwarf_wR2:
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return "wR2";
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case dwarf_wR3:
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return "wR3";
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case dwarf_wR4:
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return "wR4";
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case dwarf_wR5:
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return "wR5";
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case dwarf_wR6:
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return "wR6";
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case dwarf_wR7:
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return "wR7";
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case dwarf_wR8:
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return "wR8";
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case dwarf_wR9:
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return "wR9";
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case dwarf_wR10:
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return "wR10";
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case dwarf_wR11:
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return "wR11";
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case dwarf_wR12:
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return "wR12";
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case dwarf_wR13:
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return "wR13";
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case dwarf_wR14:
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return "wR14";
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case dwarf_wR15:
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return "wR15";
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case dwarf_spsr:
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return "spsr";
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case dwarf_spsr_fiq:
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return "spsr_fiq";
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case dwarf_spsr_irq:
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return "spsr_irq";
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case dwarf_spsr_abt:
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return "spsr_abt";
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case dwarf_spsr_und:
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return "spsr_und";
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case dwarf_spsr_svc:
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return "spsr_svc";
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case dwarf_r8_usr:
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return "r8_usr";
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case dwarf_r9_usr:
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return "r9_usr";
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case dwarf_r10_usr:
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return "r10_usr";
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case dwarf_r11_usr:
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return "r11_usr";
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case dwarf_r12_usr:
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return "r12_usr";
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case dwarf_r13_usr:
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return "r13_usr";
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case dwarf_r14_usr:
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return "r14_usr";
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case dwarf_r8_fiq:
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return "r8_fiq";
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case dwarf_r9_fiq:
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return "r9_fiq";
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case dwarf_r10_fiq:
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return "r10_fiq";
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case dwarf_r11_fiq:
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return "r11_fiq";
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case dwarf_r12_fiq:
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return "r12_fiq";
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case dwarf_r13_fiq:
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return "r13_fiq";
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case dwarf_r14_fiq:
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return "r14_fiq";
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case dwarf_r13_irq:
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return "r13_irq";
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case dwarf_r14_irq:
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return "r14_irq";
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case dwarf_r13_abt:
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return "r13_abt";
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case dwarf_r14_abt:
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return "r14_abt";
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case dwarf_r13_und:
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return "r13_und";
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case dwarf_r14_und:
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return "r14_und";
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case dwarf_r13_svc:
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return "r13_svc";
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case dwarf_r14_svc:
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return "r14_svc";
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// Intel wireless MMX control register in co-processor 0 - 7
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case dwarf_wC0:
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return "wC0";
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case dwarf_wC1:
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return "wC1";
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case dwarf_wC2:
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return "wC2";
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case dwarf_wC3:
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return "wC3";
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case dwarf_wC4:
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return "wC4";
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case dwarf_wC5:
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return "wC5";
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case dwarf_wC6:
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return "wC6";
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case dwarf_wC7:
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return "wC7";
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// VFP-v3/Neon
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case dwarf_d0:
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return "d0";
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case dwarf_d1:
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return "d1";
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case dwarf_d2:
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return "d2";
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case dwarf_d3:
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return "d3";
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case dwarf_d4:
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return "d4";
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case dwarf_d5:
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return "d5";
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case dwarf_d6:
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return "d6";
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case dwarf_d7:
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return "d7";
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case dwarf_d8:
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return "d8";
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case dwarf_d9:
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return "d9";
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case dwarf_d10:
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return "d10";
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case dwarf_d11:
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return "d11";
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case dwarf_d12:
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return "d12";
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case dwarf_d13:
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return "d13";
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case dwarf_d14:
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return "d14";
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case dwarf_d15:
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return "d15";
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case dwarf_d16:
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return "d16";
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case dwarf_d17:
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return "d17";
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case dwarf_d18:
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return "d18";
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case dwarf_d19:
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return "d19";
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case dwarf_d20:
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return "d20";
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case dwarf_d21:
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return "d21";
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case dwarf_d22:
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return "d22";
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case dwarf_d23:
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return "d23";
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case dwarf_d24:
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return "d24";
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case dwarf_d25:
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return "d25";
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case dwarf_d26:
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return "d26";
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case dwarf_d27:
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return "d27";
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case dwarf_d28:
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return "d28";
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case dwarf_d29:
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return "d29";
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case dwarf_d30:
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return "d30";
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case dwarf_d31:
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return "d31";
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// NEON 128-bit vector registers (overlays the d registers)
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case dwarf_q0:
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return "q0";
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case dwarf_q1:
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return "q1";
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case dwarf_q2:
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return "q2";
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case dwarf_q3:
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return "q3";
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case dwarf_q4:
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return "q4";
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case dwarf_q5:
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return "q5";
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case dwarf_q6:
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return "q6";
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case dwarf_q7:
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return "q7";
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case dwarf_q8:
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return "q8";
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case dwarf_q9:
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return "q9";
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case dwarf_q10:
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return "q10";
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case dwarf_q11:
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return "q11";
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case dwarf_q12:
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return "q12";
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case dwarf_q13:
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return "q13";
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case dwarf_q14:
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return "q14";
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case dwarf_q15:
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return "q15";
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}
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return nullptr;
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}
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bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo ®_info) {
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::memset(®_info, 0, sizeof(RegisterInfo));
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::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
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if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
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reg_info.byte_size = 16;
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reg_info.format = eFormatVectorOfUInt8;
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reg_info.encoding = eEncodingVector;
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}
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if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
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reg_info.byte_size = 8;
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reg_info.format = eFormatFloat;
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reg_info.encoding = eEncodingIEEE754;
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} else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) {
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reg_info.byte_size = 4;
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reg_info.format = eFormatFloat;
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reg_info.encoding = eEncodingIEEE754;
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} else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) {
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reg_info.byte_size = 12;
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reg_info.format = eFormatFloat;
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reg_info.encoding = eEncodingIEEE754;
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} else {
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reg_info.byte_size = 4;
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reg_info.format = eFormatHex;
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reg_info.encoding = eEncodingUint;
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}
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reg_info.kinds[eRegisterKindDWARF] = reg_num;
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switch (reg_num) {
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case dwarf_r0:
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reg_info.name = "r0";
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break;
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case dwarf_r1:
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reg_info.name = "r1";
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break;
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case dwarf_r2:
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reg_info.name = "r2";
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break;
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case dwarf_r3:
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reg_info.name = "r3";
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break;
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case dwarf_r4:
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reg_info.name = "r4";
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break;
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case dwarf_r5:
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reg_info.name = "r5";
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break;
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case dwarf_r6:
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reg_info.name = "r6";
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break;
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case dwarf_r7:
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reg_info.name = "r7";
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reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
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break;
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case dwarf_r8:
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reg_info.name = "r8";
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break;
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case dwarf_r9:
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reg_info.name = "r9";
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break;
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case dwarf_r10:
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reg_info.name = "r10";
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break;
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case dwarf_r11:
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reg_info.name = "r11";
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break;
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case dwarf_r12:
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reg_info.name = "r12";
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break;
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case dwarf_sp:
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reg_info.name = "sp";
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reg_info.alt_name = "r13";
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reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
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break;
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case dwarf_lr:
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reg_info.name = "lr";
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reg_info.alt_name = "r14";
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reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
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break;
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case dwarf_pc:
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reg_info.name = "pc";
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reg_info.alt_name = "r15";
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reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
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break;
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case dwarf_cpsr:
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reg_info.name = "cpsr";
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reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
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break;
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case dwarf_s0:
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reg_info.name = "s0";
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break;
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case dwarf_s1:
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reg_info.name = "s1";
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break;
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case dwarf_s2:
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reg_info.name = "s2";
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break;
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case dwarf_s3:
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reg_info.name = "s3";
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break;
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case dwarf_s4:
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reg_info.name = "s4";
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break;
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case dwarf_s5:
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reg_info.name = "s5";
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break;
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case dwarf_s6:
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reg_info.name = "s6";
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break;
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case dwarf_s7:
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reg_info.name = "s7";
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break;
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case dwarf_s8:
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reg_info.name = "s8";
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break;
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case dwarf_s9:
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reg_info.name = "s9";
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break;
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case dwarf_s10:
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reg_info.name = "s10";
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break;
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case dwarf_s11:
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reg_info.name = "s11";
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break;
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case dwarf_s12:
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reg_info.name = "s12";
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break;
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case dwarf_s13:
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reg_info.name = "s13";
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break;
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case dwarf_s14:
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reg_info.name = "s14";
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break;
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case dwarf_s15:
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reg_info.name = "s15";
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break;
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case dwarf_s16:
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reg_info.name = "s16";
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break;
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case dwarf_s17:
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reg_info.name = "s17";
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break;
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case dwarf_s18:
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reg_info.name = "s18";
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break;
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case dwarf_s19:
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reg_info.name = "s19";
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break;
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case dwarf_s20:
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reg_info.name = "s20";
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break;
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case dwarf_s21:
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reg_info.name = "s21";
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break;
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case dwarf_s22:
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reg_info.name = "s22";
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break;
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case dwarf_s23:
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reg_info.name = "s23";
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break;
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case dwarf_s24:
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reg_info.name = "s24";
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break;
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case dwarf_s25:
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reg_info.name = "s25";
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break;
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case dwarf_s26:
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reg_info.name = "s26";
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break;
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case dwarf_s27:
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reg_info.name = "s27";
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break;
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case dwarf_s28:
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reg_info.name = "s28";
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break;
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case dwarf_s29:
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reg_info.name = "s29";
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break;
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case dwarf_s30:
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reg_info.name = "s30";
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break;
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case dwarf_s31:
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reg_info.name = "s31";
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break;
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// FPA Registers 0-7
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case dwarf_f0:
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reg_info.name = "f0";
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break;
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case dwarf_f1:
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|
reg_info.name = "f1";
|
|
break;
|
|
case dwarf_f2:
|
|
reg_info.name = "f2";
|
|
break;
|
|
case dwarf_f3:
|
|
reg_info.name = "f3";
|
|
break;
|
|
case dwarf_f4:
|
|
reg_info.name = "f4";
|
|
break;
|
|
case dwarf_f5:
|
|
reg_info.name = "f5";
|
|
break;
|
|
case dwarf_f6:
|
|
reg_info.name = "f6";
|
|
break;
|
|
case dwarf_f7:
|
|
reg_info.name = "f7";
|
|
break;
|
|
|
|
// Intel wireless MMX general purpose registers 0 - 7
|
|
// XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
|
|
case dwarf_wCGR0:
|
|
reg_info.name = "wCGR0/ACC0";
|
|
break;
|
|
case dwarf_wCGR1:
|
|
reg_info.name = "wCGR1/ACC1";
|
|
break;
|
|
case dwarf_wCGR2:
|
|
reg_info.name = "wCGR2/ACC2";
|
|
break;
|
|
case dwarf_wCGR3:
|
|
reg_info.name = "wCGR3/ACC3";
|
|
break;
|
|
case dwarf_wCGR4:
|
|
reg_info.name = "wCGR4/ACC4";
|
|
break;
|
|
case dwarf_wCGR5:
|
|
reg_info.name = "wCGR5/ACC5";
|
|
break;
|
|
case dwarf_wCGR6:
|
|
reg_info.name = "wCGR6/ACC6";
|
|
break;
|
|
case dwarf_wCGR7:
|
|
reg_info.name = "wCGR7/ACC7";
|
|
break;
|
|
|
|
// Intel wireless MMX data registers 0 - 15
|
|
case dwarf_wR0:
|
|
reg_info.name = "wR0";
|
|
break;
|
|
case dwarf_wR1:
|
|
reg_info.name = "wR1";
|
|
break;
|
|
case dwarf_wR2:
|
|
reg_info.name = "wR2";
|
|
break;
|
|
case dwarf_wR3:
|
|
reg_info.name = "wR3";
|
|
break;
|
|
case dwarf_wR4:
|
|
reg_info.name = "wR4";
|
|
break;
|
|
case dwarf_wR5:
|
|
reg_info.name = "wR5";
|
|
break;
|
|
case dwarf_wR6:
|
|
reg_info.name = "wR6";
|
|
break;
|
|
case dwarf_wR7:
|
|
reg_info.name = "wR7";
|
|
break;
|
|
case dwarf_wR8:
|
|
reg_info.name = "wR8";
|
|
break;
|
|
case dwarf_wR9:
|
|
reg_info.name = "wR9";
|
|
break;
|
|
case dwarf_wR10:
|
|
reg_info.name = "wR10";
|
|
break;
|
|
case dwarf_wR11:
|
|
reg_info.name = "wR11";
|
|
break;
|
|
case dwarf_wR12:
|
|
reg_info.name = "wR12";
|
|
break;
|
|
case dwarf_wR13:
|
|
reg_info.name = "wR13";
|
|
break;
|
|
case dwarf_wR14:
|
|
reg_info.name = "wR14";
|
|
break;
|
|
case dwarf_wR15:
|
|
reg_info.name = "wR15";
|
|
break;
|
|
|
|
case dwarf_spsr:
|
|
reg_info.name = "spsr";
|
|
break;
|
|
case dwarf_spsr_fiq:
|
|
reg_info.name = "spsr_fiq";
|
|
break;
|
|
case dwarf_spsr_irq:
|
|
reg_info.name = "spsr_irq";
|
|
break;
|
|
case dwarf_spsr_abt:
|
|
reg_info.name = "spsr_abt";
|
|
break;
|
|
case dwarf_spsr_und:
|
|
reg_info.name = "spsr_und";
|
|
break;
|
|
case dwarf_spsr_svc:
|
|
reg_info.name = "spsr_svc";
|
|
break;
|
|
|
|
case dwarf_r8_usr:
|
|
reg_info.name = "r8_usr";
|
|
break;
|
|
case dwarf_r9_usr:
|
|
reg_info.name = "r9_usr";
|
|
break;
|
|
case dwarf_r10_usr:
|
|
reg_info.name = "r10_usr";
|
|
break;
|
|
case dwarf_r11_usr:
|
|
reg_info.name = "r11_usr";
|
|
break;
|
|
case dwarf_r12_usr:
|
|
reg_info.name = "r12_usr";
|
|
break;
|
|
case dwarf_r13_usr:
|
|
reg_info.name = "r13_usr";
|
|
break;
|
|
case dwarf_r14_usr:
|
|
reg_info.name = "r14_usr";
|
|
break;
|
|
case dwarf_r8_fiq:
|
|
reg_info.name = "r8_fiq";
|
|
break;
|
|
case dwarf_r9_fiq:
|
|
reg_info.name = "r9_fiq";
|
|
break;
|
|
case dwarf_r10_fiq:
|
|
reg_info.name = "r10_fiq";
|
|
break;
|
|
case dwarf_r11_fiq:
|
|
reg_info.name = "r11_fiq";
|
|
break;
|
|
case dwarf_r12_fiq:
|
|
reg_info.name = "r12_fiq";
|
|
break;
|
|
case dwarf_r13_fiq:
|
|
reg_info.name = "r13_fiq";
|
|
break;
|
|
case dwarf_r14_fiq:
|
|
reg_info.name = "r14_fiq";
|
|
break;
|
|
case dwarf_r13_irq:
|
|
reg_info.name = "r13_irq";
|
|
break;
|
|
case dwarf_r14_irq:
|
|
reg_info.name = "r14_irq";
|
|
break;
|
|
case dwarf_r13_abt:
|
|
reg_info.name = "r13_abt";
|
|
break;
|
|
case dwarf_r14_abt:
|
|
reg_info.name = "r14_abt";
|
|
break;
|
|
case dwarf_r13_und:
|
|
reg_info.name = "r13_und";
|
|
break;
|
|
case dwarf_r14_und:
|
|
reg_info.name = "r14_und";
|
|
break;
|
|
case dwarf_r13_svc:
|
|
reg_info.name = "r13_svc";
|
|
break;
|
|
case dwarf_r14_svc:
|
|
reg_info.name = "r14_svc";
|
|
break;
|
|
|
|
// Intel wireless MMX control register in co-processor 0 - 7
|
|
case dwarf_wC0:
|
|
reg_info.name = "wC0";
|
|
break;
|
|
case dwarf_wC1:
|
|
reg_info.name = "wC1";
|
|
break;
|
|
case dwarf_wC2:
|
|
reg_info.name = "wC2";
|
|
break;
|
|
case dwarf_wC3:
|
|
reg_info.name = "wC3";
|
|
break;
|
|
case dwarf_wC4:
|
|
reg_info.name = "wC4";
|
|
break;
|
|
case dwarf_wC5:
|
|
reg_info.name = "wC5";
|
|
break;
|
|
case dwarf_wC6:
|
|
reg_info.name = "wC6";
|
|
break;
|
|
case dwarf_wC7:
|
|
reg_info.name = "wC7";
|
|
break;
|
|
|
|
// VFP-v3/Neon
|
|
case dwarf_d0:
|
|
reg_info.name = "d0";
|
|
break;
|
|
case dwarf_d1:
|
|
reg_info.name = "d1";
|
|
break;
|
|
case dwarf_d2:
|
|
reg_info.name = "d2";
|
|
break;
|
|
case dwarf_d3:
|
|
reg_info.name = "d3";
|
|
break;
|
|
case dwarf_d4:
|
|
reg_info.name = "d4";
|
|
break;
|
|
case dwarf_d5:
|
|
reg_info.name = "d5";
|
|
break;
|
|
case dwarf_d6:
|
|
reg_info.name = "d6";
|
|
break;
|
|
case dwarf_d7:
|
|
reg_info.name = "d7";
|
|
break;
|
|
case dwarf_d8:
|
|
reg_info.name = "d8";
|
|
break;
|
|
case dwarf_d9:
|
|
reg_info.name = "d9";
|
|
break;
|
|
case dwarf_d10:
|
|
reg_info.name = "d10";
|
|
break;
|
|
case dwarf_d11:
|
|
reg_info.name = "d11";
|
|
break;
|
|
case dwarf_d12:
|
|
reg_info.name = "d12";
|
|
break;
|
|
case dwarf_d13:
|
|
reg_info.name = "d13";
|
|
break;
|
|
case dwarf_d14:
|
|
reg_info.name = "d14";
|
|
break;
|
|
case dwarf_d15:
|
|
reg_info.name = "d15";
|
|
break;
|
|
case dwarf_d16:
|
|
reg_info.name = "d16";
|
|
break;
|
|
case dwarf_d17:
|
|
reg_info.name = "d17";
|
|
break;
|
|
case dwarf_d18:
|
|
reg_info.name = "d18";
|
|
break;
|
|
case dwarf_d19:
|
|
reg_info.name = "d19";
|
|
break;
|
|
case dwarf_d20:
|
|
reg_info.name = "d20";
|
|
break;
|
|
case dwarf_d21:
|
|
reg_info.name = "d21";
|
|
break;
|
|
case dwarf_d22:
|
|
reg_info.name = "d22";
|
|
break;
|
|
case dwarf_d23:
|
|
reg_info.name = "d23";
|
|
break;
|
|
case dwarf_d24:
|
|
reg_info.name = "d24";
|
|
break;
|
|
case dwarf_d25:
|
|
reg_info.name = "d25";
|
|
break;
|
|
case dwarf_d26:
|
|
reg_info.name = "d26";
|
|
break;
|
|
case dwarf_d27:
|
|
reg_info.name = "d27";
|
|
break;
|
|
case dwarf_d28:
|
|
reg_info.name = "d28";
|
|
break;
|
|
case dwarf_d29:
|
|
reg_info.name = "d29";
|
|
break;
|
|
case dwarf_d30:
|
|
reg_info.name = "d30";
|
|
break;
|
|
case dwarf_d31:
|
|
reg_info.name = "d31";
|
|
break;
|
|
|
|
// NEON 128-bit vector registers (overlays the d registers)
|
|
case dwarf_q0:
|
|
reg_info.name = "q0";
|
|
break;
|
|
case dwarf_q1:
|
|
reg_info.name = "q1";
|
|
break;
|
|
case dwarf_q2:
|
|
reg_info.name = "q2";
|
|
break;
|
|
case dwarf_q3:
|
|
reg_info.name = "q3";
|
|
break;
|
|
case dwarf_q4:
|
|
reg_info.name = "q4";
|
|
break;
|
|
case dwarf_q5:
|
|
reg_info.name = "q5";
|
|
break;
|
|
case dwarf_q6:
|
|
reg_info.name = "q6";
|
|
break;
|
|
case dwarf_q7:
|
|
reg_info.name = "q7";
|
|
break;
|
|
case dwarf_q8:
|
|
reg_info.name = "q8";
|
|
break;
|
|
case dwarf_q9:
|
|
reg_info.name = "q9";
|
|
break;
|
|
case dwarf_q10:
|
|
reg_info.name = "q10";
|
|
break;
|
|
case dwarf_q11:
|
|
reg_info.name = "q11";
|
|
break;
|
|
case dwarf_q12:
|
|
reg_info.name = "q12";
|
|
break;
|
|
case dwarf_q13:
|
|
reg_info.name = "q13";
|
|
break;
|
|
case dwarf_q14:
|
|
reg_info.name = "q14";
|
|
break;
|
|
case dwarf_q15:
|
|
reg_info.name = "q15";
|
|
break;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|