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Joel Jones 6513405735 [AArch64] ILP32 Backend Relocation Support 
Remove "_NC" suffix and semantics from TLSDESC_LD{64,32}_LO12 and
  TLSDESC_ADD_LO12 relocations
Rearrange ordering in AArch64.def to follow relocation encoding
Fix name:
  R_AARCH64_P32_LD64_GOT_LO12_NC => R_AARCH64_P32_LD32_GOT_LO12_NC
Add support for several "TLS", "TLSGD", and "TLSLD" relocations for
  ILP32
Fix return values from isNonILP32reloc
Add implementations for
  R_AARCH64_ADR_PREL_PG_HI21_NC, R_AARCH64_P32_LD32_GOT_LO12_NC,
  R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC,
  R_AARCH64_P32_TLSDESC_LD32_LO12, R_AARCH64_LD64_GOT_LO12_NC,
  *TLSLD_LDST128_DTPREL_LO12, *TLSLD_LDST128_DTPREL_LO12_NC,
  *TLSLE_LDST128_TPREL_LO12, *TLSLE_LDST128_TPREL_LO12_NC
Modify error messages to give name of equivalent relocation in the
  ABI not being used, along with better checking for non-existent
  requested relocations.
Added assembler support for "pg_hi21_nc"
Relocation definitions added without implementations:
  R_AARCH64_P32_TLSDESC_ADR_PREL21, R_AARCH64_P32_TLSGD_ADR_PREL21,
  R_AARCH64_P32_TLSGD_ADD_LO12_NC, R_AARCH64_P32_TLSLD_ADR_PREL21, 
  R_AARCH64_P32_TLSLD_ADR_PAGE21, R_AARCH64_P32_TLSLD_ADD_LO12_NC,
  R_AARCH64_P32_TLSLD_LD_PREL19, R_AARCH64_P32_TLSDESC_LD_PREL19,
  R_AARCH64_P32_TLSGD_ADR_PAGE21, R_AARCH64_P32_TLS_DTPREL,
  R_AARCH64_P32_TLS_DTPMOD, R_AARCH64_P32_TLS_TPREL,
  R_AARCH64_P32_TLSDESC
Fix encoding:
  R_AARCH64_P32_TLSDESC_ADR_PAGE21

Reviewers: Peter Smith

Patch by: Joel Jones (jjones@cavium.com)

Differential Revision: https://reviews.llvm.org/D32072

llvm-svn: 301980
 		2017-05-02 22:01:48 +00:00
..
AsmParser [Arch64AsmParser] better diagnostic for isb 2017-04-24 08:22:20 +00:00
Disassembler [AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-01-06 00:30:53 +00:00
InstPrinter AArch64: lower "fence singlethread" to a pure compiler barrier. 2017-04-20 21:57:45 +00:00
MCTargetDesc [AArch64] ILP32 Backend Relocation Support 2017-05-02 22:01:48 +00:00
TargetInfo
…
Utils [AArch64AsmParser] rewrite of function parseSysAlias 2017-03-03 08:12:47 +00:00
AArch64.h [globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces 2017-04-06 09:49:34 +00:00
AArch64.td [AArch64] Crypto requires FP. 2017-04-05 10:44:38 +00:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp LiveRegUnits: Add accumulateBackward() function 2017-01-21 02:21:04 +00:00
AArch64AddressTypePromotion.cpp [AArch64] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-01-25 00:29:26 +00:00
AArch64AdvSIMDScalarPass.cpp
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AArch64AsmPrinter.cpp [AArch64] ILP32 Backend Relocation Support 2017-05-02 22:01:48 +00:00
AArch64CallLowering.cpp Rename AttributeSet to AttributeList 2017-03-21 16:57:19 +00:00
AArch64CallLowering.h [GlobalISel] Use the correct calling conv for calls 2017-03-20 14:40:18 +00:00
AArch64CallingConvention.h
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AArch64CallingConvention.td SwiftCC: swifterror register cannot be as the base register 2017-02-09 01:52:17 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp AArch64CollectLOH: Rewrite as block-local analysis. 2017-01-06 19:22:01 +00:00
AArch64ConditionOptimizer.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
AArch64ConditionalCompares.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
AArch64DeadRegisterDefinitionsPass.cpp AArch64: Use DeadRegisterDefinitionsPass before regalloc. 2016-11-16 03:38:27 +00:00
AArch64ExpandPseudoInsts.cpp AArch64: lower "fence singlethread" to a pure compiler barrier. 2017-04-20 21:57:45 +00:00
AArch64FastISel.cpp Use Argument::hasAttribute and AttributeList::ReturnIndex more 2017-04-28 18:37:16 +00:00
AArch64FrameLowering.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
AArch64FrameLowering.h
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AArch64GenRegisterBankInfo.def GlobalISel: fall back gracefully when we can't map an operand's size. 2017-02-06 21:57:06 +00:00
AArch64ISelDAGToDAG.cpp [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDemandedBits 2017-04-28 05:31:46 +00:00
AArch64ISelLowering.cpp Generalize the specialized flag-carrying SDNodes by moving flags into SDNode. 2017-05-01 15:17:51 +00:00
AArch64ISelLowering.h [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDemandedBits 2017-04-28 05:31:46 +00:00
AArch64InstrAtomics.td AArch64: lower "fence singlethread" to a pure compiler barrier. 2017-04-20 21:57:45 +00:00
AArch64InstrFormats.td [globalisel][tablegen] Revise API for ComplexPattern operands to improve flexibility. 2017-04-22 15:11:04 +00:00
AArch64InstrInfo.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
AArch64InstrInfo.h Re-commit r301040 "X86: Don't emit zero-byte functions on Windows" 2017-04-21 21:48:41 +00:00
AArch64InstrInfo.td [globalisel][tablegen] Compute available feature bits correctly. 2017-04-29 17:30:09 +00:00
AArch64InstructionSelector.cpp [globalisel][tablegen] Compute available feature bits correctly. 2017-04-29 17:30:09 +00:00
AArch64LegalizerInfo.cpp GlobalISel: constrain G_INSERT to inserting just one value per instruction. 2017-03-03 23:05:47 +00:00
AArch64LegalizerInfo.h GlobalISel: legalize va_arg on AArch64. 2017-02-15 23:22:50 +00:00
AArch64LoadStoreOptimizer.cpp [AArch64] Use alias analysis in the load/store optimization pass. 2017-03-17 14:19:55 +00:00
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
…
AArch64MachineFunctionInfo.h [AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-01-06 00:30:53 +00:00
AArch64MacroFusion.cpp [AArch64] Simplify MacroFusion 2017-04-11 19:13:11 +00:00
AArch64MacroFusion.h [CodeGen] Move MacroFusion to the target 2017-02-01 02:54:34 +00:00
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PromoteConstant.cpp
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AArch64RedundantCopyElimination.cpp [AArch64][Redundant Copy Elim] Add support for CMN and shifted imm. 2017-03-06 21:20:00 +00:00
AArch64RegisterBankInfo.cpp [GlobalISel] Support vector-of-pointers in LLT 2017-04-19 07:23:57 +00:00
AArch64RegisterBankInfo.h GlobalISel: fall back gracefully when we can't map an operand's size. 2017-02-06 21:57:06 +00:00
AArch64RegisterBanks.td Re-commit: [globalisel] Tablegen-erate current Register Bank Information 2017-01-19 11:15:55 +00:00
AArch64RegisterInfo.cpp AArch64RegisterInfo: Simplify getReservedReg(); NFC 2017-02-02 02:23:25 +00:00
AArch64RegisterInfo.h AArch64: Enable post-ra liveness updates 2016-12-16 23:55:43 +00:00
AArch64RegisterInfo.td [AArch64] Corrected spill size for DDD register class. NFCI 2016-10-21 09:53:42 +00:00
AArch64SchedA53.td [MachineScheduler] Reference the correct header. 2017-03-26 21:27:21 +00:00
AArch64SchedA57.td [AArch64] Add new subtarget feature to fuse AES crypto operations 2017-02-01 02:54:39 +00:00
AArch64SchedA57WriteRes.td [AArch64] Cortex-A57 FDIV/FSQRT scheduling fix (W-unit) 2016-12-23 12:51:41 +00:00
AArch64SchedCyclone.td
…
AArch64SchedFalkor.td [AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892. 2017-04-21 13:37:01 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Refine modeling of store-release exclusive instructions. 2017-04-21 14:58:32 +00:00
AArch64SchedFalkorWriteRes.td [AArch64][Falkor] Refine modeling of store-release exclusive instructions. 2017-04-21 14:58:32 +00:00
AArch64SchedKryo.td
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AArch64SchedKryoDetails.td [AArch64] Refine Kryo Machine Model 2017-01-26 20:10:41 +00:00
AArch64SchedM1.td [AArch64] Add new subtarget feature to fuse AES crypto operations 2017-02-01 02:54:39 +00:00
AArch64SchedThunderX.td [AArch64] Vulcan is now ThunderXT99 2017-03-07 19:42:40 +00:00
AArch64SchedThunderX2T99.td [AArch64] Vulcan is now ThunderXT99 2017-03-07 19:42:40 +00:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp [AArch64] Drive-by cleanup, make this code shorter. NFCI. 2017-03-22 23:37:58 +00:00
AArch64SelectionDAGInfo.h
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp [AArch64] Move GISel accessor initialization from TargetMachine to Subtarget. 2017-05-01 21:53:19 +00:00
AArch64Subtarget.h [globalisel][tablegen] Compute available feature bits correctly. 2017-04-29 17:30:09 +00:00
AArch64SystemOperands.td AArch64InstPrinter: rewrite of printSysAlias 2017-02-27 14:45:34 +00:00
AArch64TargetMachine.cpp [AArch64] Move GISel accessor initialization from TargetMachine to Subtarget. 2017-05-01 21:53:19 +00:00
AArch64TargetMachine.h [globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces 2017-04-06 09:49:34 +00:00
AArch64TargetObjectFile.cpp CodeGen: simplify TargetMachine::getSymbol interface. NFC. 2016-11-22 16:17:20 +00:00
AArch64TargetObjectFile.h
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AArch64TargetTransformInfo.cpp [SystemZ] TargetTransformInfo cost functions implemented. 2017-04-12 11:49:08 +00:00
AArch64TargetTransformInfo.h [SystemZ] TargetTransformInfo cost functions implemented. 2017-04-12 11:49:08 +00:00
AArch64VectorByElementOpt.cpp [AArch64] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-01-25 00:29:26 +00:00
CMakeLists.txt [CodeGen] Move MacroFusion to the target 2017-02-01 02:54:34 +00:00
LLVMBuild.txt
…