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Alex Bradbury 6a53023b4e [RISCV] Set isReMaterializable on ADDI and LUI instructions 
The isReMaterlizable flag is somewhat confusing, unlike most other instruction 
flags it is currently interpreted as a hint (mightBeRematerializable would be 
a better name). While LUI is always rematerialisable, for an instruction like 
ADDI it depends on its operands. TargetInstrInfo::isTriviallyReMaterializable 
will call TargetInstrInfo::isReallyTriviallyReMaterializable, which in turn 
calls TargetInstrInfo::isReallyTriviallyReMaterializableGeneric. We rely on 
the logic in the latter to pick out instances of ADDI that really are 
rematerializable.

The isReMaterializable flag does make a difference on a variety of test 
programs. The recently committed remat.ll test case demonstrates how stack 
usage is reduce and a unnecessary lw/sw can be removed. Stack usage in the 
Proc0 function in dhrystone reduces from 192 bytes to 112 bytes.

For the sake of completeness, this patch also implements 
RISCVRegisterInfo::isConstantPhysReg. Although this is called from a number of 
places, it doesn't seem to result in different codegen for any programs I've 
thrown at it. However, it is called in the rematerialisation codepath and it 
seems sensible to implement something correct here.

Differential Revision: https://reviews.llvm.org/D46182

llvm-svn: 332617
 		2018-05-17 15:51:37 +00:00
..
addc-adde-sube-subc.ll
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align.ll [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC 2018-04-12 11:30:59 +00:00
alloca.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
alu32.ll [RISCV] Expand codegen -> compression sanity checks and move to a single file 2018-04-18 20:17:29 +00:00
analyze-branch.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
bare-select.ll [RISCV] Codegen support for RV32F floating point comparison operations 2018-03-21 15:11:02 +00:00
blockaddress.ll [RISCV] Peephole optimisation for load/store of global values or constant addresses 2018-03-19 11:54:28 +00:00
branch-relaxation.ll
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branch.ll [RISCV] Expand codegen -> compression sanity checks and move to a single file 2018-04-18 20:17:29 +00:00
bswap-ctlz-cttz-ctpop.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
byval.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
calling-conv-sext-zext.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
calling-conv.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
calls.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
compress-inline-asm.ll [RISCV] Tablegen-driven Instruction Compression. 2018-04-06 21:07:05 +00:00
compress.ll [RISCV] Add test changes missed from rL330293 2018-04-18 20:36:12 +00:00
div.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-arith.ll [RISCV] Add codegen support for RV32D floating point arithmetic operations 2018-04-12 05:42:42 +00:00
double-br-fcmp.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-calling-conv.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-convert.ll [RISCV] Codegen support for RV32D floating point conversion operations 2018-04-12 05:47:15 +00:00
double-fcmp.ll [RISCV] Codegen support for RV32D floating point comparison operations 2018-04-12 05:50:06 +00:00
double-imm.ll [RISCV] Add tests missed in r329871 2018-04-12 05:36:44 +00:00
double-intrinsics.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-mem.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-previous-failure.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
double-select-fcmp.ll [RISCV] Codegen support for RV32D floating point comparison operations 2018-04-12 05:50:06 +00:00
double-stack-spill-restore.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
float-arith.ll [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits 2018-04-18 20:34:23 +00:00
float-br-fcmp.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
float-convert.ll [RISCV] Add codegen for RV32F arithmetic and conversion operations 2018-03-20 12:45:35 +00:00
float-fcmp.ll [RISCV] Codegen support for RV32F floating point comparison operations 2018-03-21 15:11:02 +00:00
float-imm.ll [RISCV] Add codegen for RV32F floating point load/store 2018-03-20 13:26:12 +00:00
float-mem.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
float-select-fcmp.ll [RISCV] Codegen support for RV32F floating point comparison operations 2018-03-21 15:11:02 +00:00
fp128.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
frame.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
frameaddr-returnaddr.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
get-setcc-result-type.ll
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i32-icmp.ll
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imm-cse.ll [RISCV] Add imm-cse.ll test case 2018-04-18 20:25:07 +00:00
imm.ll [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits 2018-04-18 20:34:23 +00:00
indirectbr.ll
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init-array.ll [RISCV] Use init_array instead of ctors for RISCV target, by default 2018-03-24 18:37:19 +00:00
inline-asm.ll [RISCV] Peephole optimisation for load/store of global values or constant addresses 2018-03-19 11:54:28 +00:00
jumptable.ll
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large-stack.ll
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lit.local.cfg
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lsr-legaladdimm.ll [RISCV] Implement isLegalAddImmediate 2018-04-26 13:00:37 +00:00
mem.ll [RISCV] Peephole optimisation for load/store of global values or constant addresses 2018-03-19 11:54:28 +00:00
mul.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
option-norvc.ll [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
option-rvc.ll [RISCV] Support .option rvc and norvc assembler directives 2018-05-11 17:30:28 +00:00
rem.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
remat.ll [RISCV] Set isReMaterializable on ADDI and LUI instructions 2018-05-17 15:51:37 +00:00
rotl-rotr.ll
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select-cc.ll
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sext-zext-trunc.ll
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shifts.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
vararg.ll [RISCV] Expand function call to "call" pseudoinstruction 2018-04-25 14:19:12 +00:00
wide-mem.ll [RISCV] Peephole optimisation for load/store of global values or constant addresses 2018-03-19 11:54:28 +00:00
zext-with-load-is-free.ll [RISCV] Implement isZextFree 2018-04-26 14:04:18 +00:00