80 lines
3.3 KiB
TableGen
80 lines
3.3 KiB
TableGen
//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mips64 Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasMips64 : Predicate<"Subtarget.hasMips64()">;
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def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def simm16_64 : Operand<i64>;
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// Unsigned Operand
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Arithmetic 3 register operands
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class ArithR64<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin, bit isComm = 0>:
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FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], itin> {
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let isCommutable = isComm;
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}
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// Arithmetic 2 register operands
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class ArithI64<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, imm_type:$c))], IIAlu>;
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// Logical
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let isCommutable = 1 in
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class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>:
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FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu>;
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class LogicI64<bits<6> op, string instr_asm, SDNode OpNode>:
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FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, uimm16_64:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>;
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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def DADDiu : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
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def DANDi : LogicI64<0x0c, "andi", and>;
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def DORi : LogicI64<0x0d, "ori", or>;
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def DXORi : LogicI64<0x0e, "xori", xor>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADDu : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
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def DSUBu : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu, 1>;
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def DAND : LogicR64<0x24, "and", and>;
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def DOR : LogicR64<0x25, "or", or>;
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def DXOR : LogicR64<0x26, "xor", xor>;
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