446 lines
14 KiB
C++
446 lines
14 KiB
C++
//===-- ArmUnwindInfo.cpp ---------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include <vector>
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#include "lldb/Core/Module.h"
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#include "lldb/Core/Section.h"
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#include "lldb/Host/Endian.h"
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#include "lldb/Symbol/ArmUnwindInfo.h"
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#include "lldb/Symbol/SymbolVendor.h"
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#include "lldb/Symbol/UnwindPlan.h"
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#include "Utility/ARM_DWARF_Registers.h"
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/*
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* Unwind information reader and parser for the ARM exception handling ABI
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*
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* Implemented based on:
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* Exception Handling ABI for the ARM Architecture
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* Document number: ARM IHI 0038A (current through ABI r2.09)
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* Date of Issue: 25th January 2007, reissued 30th November 2012
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* http://infocenter.arm.com/help/topic/com.arm.doc.ihi0038a/IHI0038A_ehabi.pdf
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*/
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using namespace lldb;
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using namespace lldb_private;
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// Converts a prel31 avlue to lldb::addr_t with sign extension
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static addr_t
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Prel31ToAddr(uint32_t prel31)
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{
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addr_t res = prel31;
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if (prel31 & (1<<30))
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res |= 0xffffffff80000000ULL;
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return res;
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}
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ArmUnwindInfo::ArmExidxEntry::ArmExidxEntry(uint32_t f, lldb::addr_t a, uint32_t d) :
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file_address(f), address(a), data(d)
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{
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}
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bool
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ArmUnwindInfo::ArmExidxEntry::operator<(const ArmExidxEntry& other) const
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{
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return address < other.address;
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}
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ArmUnwindInfo::ArmUnwindInfo(const ObjectFile& objfile,
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SectionSP& arm_exidx,
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SectionSP& arm_extab) :
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m_byte_order(objfile.GetByteOrder()),
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m_arm_exidx_sp(arm_exidx),
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m_arm_extab_sp(arm_extab)
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{
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objfile.ReadSectionData(arm_exidx.get(), m_arm_exidx_data);
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objfile.ReadSectionData(arm_extab.get(), m_arm_extab_data);
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addr_t exidx_base_addr = m_arm_exidx_sp->GetFileAddress();
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offset_t offset = 0;
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while (m_arm_exidx_data.ValidOffset(offset))
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{
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lldb::addr_t file_addr = exidx_base_addr + offset;
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lldb::addr_t addr = exidx_base_addr +
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(addr_t)offset +
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Prel31ToAddr(m_arm_exidx_data.GetU32(&offset));
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uint32_t data = m_arm_exidx_data.GetU32(&offset);
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m_exidx_entries.emplace_back(file_addr, addr, data);
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}
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// Sort the entries in the exidx section. The entries should be sorted inside the section but
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// some old compiler isn't sorted them.
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std::sort(m_exidx_entries.begin(), m_exidx_entries.end());
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}
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ArmUnwindInfo::~ArmUnwindInfo()
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{
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}
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// Read a byte from the unwind instruction stream with the given offset.
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// Custom function is required because have to red in order of significance within their containing
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// word (most significant byte first) and in increasing word address order.
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uint8_t
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ArmUnwindInfo::GetByteAtOffset(const uint32_t* data, uint16_t offset) const
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{
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uint32_t value = data[offset / 4];
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if (m_byte_order != endian::InlHostByteOrder())
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value = llvm::ByteSwap_32(value);
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return (value >> ((3 - (offset % 4)) * 8)) & 0xff;
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}
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uint64_t
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ArmUnwindInfo::GetULEB128(const uint32_t* data, uint16_t& offset, uint16_t max_offset) const
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{
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uint64_t result = 0;
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uint8_t shift = 0;
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while (offset < max_offset)
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{
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uint8_t byte = GetByteAtOffset(data, offset++);
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result |= (byte & 0x7f) << shift;
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if ((byte & 0x80) == 0)
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break;
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shift += 7;
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}
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return result;
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}
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bool
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ArmUnwindInfo::GetUnwindPlan(Target &target, const Address& addr, UnwindPlan& unwind_plan)
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{
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const uint32_t* data = (const uint32_t*)GetExceptionHandlingTableEntry(addr);
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if (data == nullptr)
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return false; // No unwind information for the function
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if (data[0] == 0x1)
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return false; // EXIDX_CANTUNWIND
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uint16_t byte_count = 0;
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uint16_t byte_offset = 0;
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if (data[0] & 0x80000000)
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{
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switch ((data[0] >> 24) & 0x0f)
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{
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case 0:
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byte_count = 4;
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byte_offset = 1;
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break;
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case 1:
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case 2:
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byte_count = 4 * ((data[0] >> 16) & 0xff) + 4;
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byte_offset = 2;
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break;
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default:
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// Unhandled personality routine index
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return false;
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}
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}
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else
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{
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byte_count = 4 * ((data[1] >> 24) & 0xff) + 8;
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byte_offset = 5;
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}
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uint8_t vsp_reg = dwarf_sp;
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int32_t vsp = 0;
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std::vector<std::pair<uint32_t, int32_t>> register_offsets; // register -> (offset from vsp_reg)
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while (byte_offset < byte_count)
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{
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uint8_t byte1 = GetByteAtOffset(data, byte_offset++);
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if ((byte1&0xc0) == 0x00)
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{
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// 00xxxxxx
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// vsp = vsp + (xxxxxx << 2) + 4. Covers range 0x04-0x100 inclusive
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vsp += ((byte1 & 0x3f) << 2) + 4;
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}
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else if ((byte1&0xc0) == 0x40)
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{
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// 01xxxxxx
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// vsp = vsp – (xxxxxx << 2) - 4. Covers range 0x04-0x100 inclusive
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vsp -= ((byte1 & 0x3f) << 2) + 4;
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}
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else if ((byte1&0xf0) == 0x80)
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{
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if (byte_offset >= byte_count)
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return false;
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uint8_t byte2 = GetByteAtOffset(data, byte_offset++);
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if (byte1 == 0x80 && byte2 == 0)
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{
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// 10000000 00000000
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// Refuse to unwind (for example, out of a cleanup) (see remark a)
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return false;
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}
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else
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{
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// 1000iiii iiiiiiii (i not all 0)
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// Pop up to 12 integer registers under masks {r15-r12}, {r11-r4} (see remark b)
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uint16_t regs = ((byte1&0x0f) << 8) | byte2;
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for (uint8_t i = 0; i < 12; ++i)
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{
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if (regs & (1<<i))
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{
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register_offsets.emplace_back(dwarf_r4 + i, vsp);
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vsp += 4;
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}
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}
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}
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}
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else if ((byte1&0xff) == 0x9d)
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{
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// 10011101
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// Reserved as prefix for ARM register to register moves
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return false;
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}
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else if ((byte1&0xff) == 0x9f)
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{
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// 10011111
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// Reserved as prefix for Intel Wireless MMX register to register moves
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return false;
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}
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else if ((byte1&0xf0) == 0x90)
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{
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// 1001nnnn (nnnn != 13,15)
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// Set vsp = r[nnnn]
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vsp_reg = dwarf_r0 + (byte1&0x0f);
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}
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else if ((byte1&0xf8) == 0xa0)
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{
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// 10100nnn
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// Pop r4-r[4+nnn]
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uint8_t n = byte1&0x7;
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for (uint8_t i = 0; i <= n; ++i)
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{
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register_offsets.emplace_back(dwarf_r4 + i, vsp);
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vsp += 4;
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}
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}
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else if ((byte1&0xf8) == 0xa8)
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{
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// 10101nnn
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// Pop r4-r[4+nnn], r14
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uint8_t n = byte1&0x7;
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for (uint8_t i = 0; i <= n; ++i)
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{
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register_offsets.emplace_back(dwarf_r4 + i, vsp);
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vsp += 4;
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}
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register_offsets.emplace_back(dwarf_lr, vsp);
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vsp += 4;
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}
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else if ((byte1&0xff) == 0xb0)
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{
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// 10110000
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// Finish (see remark c)
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break;
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}
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else if ((byte1&0xff) == 0xb1)
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{
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if (byte_offset >= byte_count)
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return false;
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uint8_t byte2 = GetByteAtOffset(data, byte_offset++);
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if ((byte2&0xff) == 0x00)
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{
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// 10110001 00000000
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// Spare (see remark f)
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return false;
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}
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else if ((byte2&0xf0) == 0x00)
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{
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// 10110001 0000iiii (i not all 0)
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// Pop integer registers under mask {r3, r2, r1, r0}
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for (uint8_t i = 0; i < 4; ++i)
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{
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if (byte2 & (1<<i))
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{
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register_offsets.emplace_back(dwarf_r0 + i, vsp);
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vsp += 4;
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}
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}
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}
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else
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{
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// 10110001 xxxxyyyy
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// Spare (xxxx != 0000)
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return false;
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}
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}
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else if ((byte1&0xff) == 0xb2)
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{
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// 10110010 uleb128
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// vsp = vsp + 0x204+ (uleb128 << 2)
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uint64_t uleb128 = GetULEB128(data, byte_offset, byte_count);
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vsp += 0x204 + (uleb128 << 2);
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}
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else if ((byte1&0xff) == 0xb3)
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{
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// 10110011 sssscccc
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// Pop VFP double-precision registers D[ssss]-D[ssss+cccc] saved (as if) by FSTMFDX (see remark d)
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if (byte_offset >= byte_count)
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return false;
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uint8_t byte2 = GetByteAtOffset(data, byte_offset++);
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uint8_t s = (byte2&0xf0) >> 4;
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uint8_t c = (byte2&0x0f) >> 0;
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for (uint8_t i = 0; i <= c; ++i)
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{
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register_offsets.emplace_back(dwarf_d0 + s + i, vsp);
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vsp += 8;
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}
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vsp += 4;
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}
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else if ((byte1&0xfc) == 0xb4)
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{
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// 101101nn
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// Spare (was Pop FPA)
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return false;
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}
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else if ((byte1&0xf8) == 0xb8)
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{
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// 10111nnn
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// Pop VFP double-precision registers D[8]-D[8+nnn] saved (as if) by FSTMFDX (see remark d)
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uint8_t n = byte1&0x07;
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for (uint8_t i = 0; i <= n; ++i)
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{
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register_offsets.emplace_back(dwarf_d8 + i, vsp);
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vsp += 8;
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}
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vsp += 4;
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}
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else if ((byte1&0xf8) == 0xc0)
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{
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// 11000nnn (nnn != 6,7)
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// Intel Wireless MMX pop wR[10]-wR[10+nnn]
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// 11000110 sssscccc
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// Intel Wireless MMX pop wR[ssss]-wR[ssss+cccc] (see remark e)
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// 11000111 00000000
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// Spare
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// 11000111 0000iiii
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// Intel Wireless MMX pop wCGR registers under mask {wCGR3,2,1,0}
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// 11000111 xxxxyyyy
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// Spare (xxxx != 0000)
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return false;
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}
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else if ((byte1&0xff) == 0xc8)
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{
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// 11001000 sssscccc
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// Pop VFP double precision registers D[16+ssss]-D[16+ssss+cccc] saved (as if) by FSTMFDD (see remarks d,e)
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if (byte_offset >= byte_count)
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return false;
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uint8_t byte2 = GetByteAtOffset(data, byte_offset++);
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uint8_t s = (byte2&0xf0) >> 4;
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uint8_t c = (byte2&0x0f) >> 0;
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for (uint8_t i = 0; i <= c; ++i)
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{
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register_offsets.emplace_back(dwarf_d16 + s + i, vsp);
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vsp += 8;
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}
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}
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else if ((byte1&0xff) == 0xc9)
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{
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// 11001001 sssscccc
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// Pop VFP double precision registers D[ssss]-D[ssss+cccc] saved (as if) by FSTMFDD (see remark d)
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if (byte_offset >= byte_count)
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return false;
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uint8_t byte2 = GetByteAtOffset(data, byte_offset++);
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uint8_t s = (byte2&0xf0) >> 4;
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uint8_t c = (byte2&0x0f) >> 0;
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for (uint8_t i = 0; i <= c; ++i)
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{
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register_offsets.emplace_back(dwarf_d0 + s + i, vsp);
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vsp += 8;
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}
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}
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else if ((byte1&0xf8) == 0xc8)
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{
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// 11001yyy
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// Spare (yyy != 000, 001)
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return false;
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}
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else if ((byte1&0xf8) == 0xc0)
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{
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// 11010nnn
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// Pop VFP double-precision registers D[8]-D[8+nnn] saved (as if) by FSTMFDD (see remark d)
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uint8_t n = byte1&0x07;
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for (uint8_t i = 0; i <= n; ++i)
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{
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register_offsets.emplace_back(dwarf_d8 + i, vsp);
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vsp += 8;
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}
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}
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else if ((byte1&0xc0) == 0xc0)
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{
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// 11xxxyyy Spare (xxx != 000, 001, 010)
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return false;
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}
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else
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{
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return false;
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}
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}
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UnwindPlan::RowSP row = std::make_shared<UnwindPlan::Row>();
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row->SetOffset(0);
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row->GetCFAValue().SetIsRegisterPlusOffset(vsp_reg, vsp);
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bool have_location_for_pc = false;
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for (const auto& offset : register_offsets)
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{
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have_location_for_pc |= offset.first == dwarf_pc;
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row->SetRegisterLocationToAtCFAPlusOffset(offset.first, offset.second - vsp, true);
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}
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if (!have_location_for_pc)
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{
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UnwindPlan::Row::RegisterLocation lr_location;
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if (row->GetRegisterInfo(dwarf_lr, lr_location))
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row->SetRegisterInfo(dwarf_pc, lr_location);
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else
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row->SetRegisterLocationToRegister(dwarf_pc, dwarf_lr, false);
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}
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unwind_plan.AppendRow(row);
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unwind_plan.SetSourceName ("ARM.exidx unwind info");
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unwind_plan.SetSourcedFromCompiler (eLazyBoolYes);
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unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolNo);
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unwind_plan.SetRegisterKind (eRegisterKindDWARF);
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return true;
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}
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const uint8_t*
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ArmUnwindInfo::GetExceptionHandlingTableEntry(const Address& addr)
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{
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auto it = std::upper_bound(m_exidx_entries.begin(),
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m_exidx_entries.end(),
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ArmExidxEntry{0, addr.GetFileAddress(), 0});
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if (it == m_exidx_entries.begin())
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return nullptr;
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--it;
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if (it->data == 0x1)
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return nullptr; // EXIDX_CANTUNWIND
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if (it->data & 0x80000000)
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return (const uint8_t*)&it->data;
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addr_t data_file_addr = it->file_address + 4 + Prel31ToAddr(it->data);
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return m_arm_extab_data.GetDataStart() + (data_file_addr - m_arm_extab_sp->GetFileAddress());
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}
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