Shiva Chen 43bfe84451 [RISCV] Support linker relax function call from auipc and jalr to jal ... To do this: 1. Add fixup_riscv_relax fixup types which eventually will transfer to R_RISCV_RELAX relocation types. 2. Insert R_RISCV_RELAX relocation types to auipc function call expression when linker relaxation enabled. Differential Revision: https://reviews.llvm.org/D44886 llvm-svn: 333158		2018-05-24 06:21:23 +00:00
..
Analysis	Fix aliasing of launder.invariant.group	2018-05-23 09:16:44 +00:00
Assembler	…
Bindings	[LLVM-C] Add DIBuilder Bindings For ObjC Classes	2018-05-21 16:27:35 +00:00
Bitcode	…
BugPoint	…
CodeGen	[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX	2018-05-24 03:20:28 +00:00
DebugInfo	Move a debug info test into the X86 directory	2018-05-23 22:50:45 +00:00
Examples	…
ExecutionEngine	[RuntimeDyld][MachO] Add support for MachO::ARM64_RELOC_POINTER_TO_GOT reloc.	2018-05-23 21:27:07 +00:00
Feature	…
FileCheck	…
Instrumentation	[msan] Don't check divisor shadow in fdiv.	2018-05-18 20:19:53 +00:00
Integer	…
JitListener	…
LTO	…
Linker	…
MC	[RISCV] Support linker relax function call from auipc and jalr to jal	2018-05-24 06:21:23 +00:00
Object	…
ObjectYAML	Resubmit [pdb] Change /DEBUG:GHASH to emit 8 byte hashes."	2018-05-17 22:55:15 +00:00
Other	Add remarks describing when a pass changes the IR instruction count of a module	2018-05-18 17:26:39 +00:00
SafepointIRVerifier	SafepointIRVerifier is made unreachable block tolerant	2018-05-23 05:54:55 +00:00
SymbolRewriter	…
TableGen	[GlobalISel][InstructionSelect] Moving Reg Bank Checks forward, perf patch 9	2018-05-23 23:58:10 +00:00
ThinLTO/X86	…
Transforms	[NaryReassociate] Detect deleted instr with WeakVH	2018-05-24 06:09:02 +00:00
Unit	…
Verifier	…
YAMLParser	…
tools	[llvm-strip] Minor fix of the usage of TableGen	2018-05-23 20:39:52 +00:00
.clang-format	…
CMakeLists.txt	…
TestRunner.sh	…
lit.cfg.py	…
lit.site.cfg.py.in	…