Johnny Chen 2cf04957c2 Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not ... follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand). Add a parent class N3Vf which requires passing a Format argument and which the N3V class is modified to inherit from. N3V class represents the "normal" 3-Register NEON Instructions with N3RegFrm. Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift Instructions and replace 8 invocations with it. llvm-svn: 99655		2010-03-26 21:26:28 +00:00
clang	When trying to determine whether one operand of a conditional	2010-03-26 20:59:55 +00:00
compiler-rt	Don't build an armv7 slice for now, it has the same stuff as on armv6.	2010-03-26 21:07:05 +00:00
llvm	Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not	2010-03-26 21:26:28 +00:00