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hanchenye-llvm-project/llvm/test/CodeGen/MIR
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Francis Visoiu Mistrih c71cced0aa [CodeGen] Always use `printReg` to print registers in both MIR and debug 
output

As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.

Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.

Differential Revision: https://reviews.llvm.org/D40421

llvm-svn: 319445
 		2017-11-30 16:12:24 +00:00
..
AArch64 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
AMDGPU MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
ARM [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
Generic [RegAllocFast] Add the proper initialize method to use the .mir infrastructure 2017-07-07 19:25:42 +00:00
Hexagon [Hexagon] Handle Hexagon-specific machine operand target flags in MIR 2017-07-10 18:31:02 +00:00
Mips
…
NVPTX MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
PowerPC
…
X86 [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.