hanchenye-llvm-project/llvm/test/CodeGen
Matthias Braun 71f9564e7f LiveIntervalAnalysis: Rework constructMainRangeFromSubranges()
We now use LiveRangeCalc::extendToUses() instead of a specially designed
algorithm in constructMainRangeFromSubranges():
- The original motivation for constructMainRangeFromSubranges() were
  differences between the main liverange and subranges because of hidden
  dead definitions. This case however cannot happen anymore with the
  DetectDeadLaneMasks pass in place.
- It simplifies the code.
- This fixes a longstanding bug where we did not properly create new SSA
  values on merging control flow (the MachineVerifier missed most of
  these cases).
- Move constructMainRangeFromSubranges() to LiveIntervalAnalysis and
  LiveRangeCalc to better match the implementation/available helper
  functions.

This re-applies r269016. The fixes from r270290 and r270259 should avoid
the machine verifier problems this time.

llvm-svn: 270291
2016-05-20 23:14:56 +00:00
..
AArch64 [AArch64] Disable narrow load merge by default 2016-05-20 18:45:49 +00:00
AMDGPU LiveIntervalAnalysis: Rework constructMainRangeFromSubranges() 2016-05-20 23:14:56 +00:00
ARM [ARM, AArch64] Match additional patterns to ldN instructions 2016-05-19 21:39:00 +00:00
BPF [llc] New diagnostic handler 2016-05-16 14:28:02 +00:00
Generic llc: Rework -run-pass option 2016-05-10 01:32:44 +00:00
Hexagon When looking for a spill slot in reg scavenger, find one that matches RC 2016-05-18 18:16:00 +00:00
Inputs [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
Lanai [lanai] Change reloc to use PIC_ by default and cleanup. 2016-05-20 21:41:53 +00:00
MIR [llc] New diagnostic handler 2016-05-16 14:28:02 +00:00
MSP430 `MSP430InstrInfo::loadRegFromStackSlot` forgets to set register def. 2016-02-24 15:15:02 +00:00
Mips [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine verifier. 2016-05-19 10:42:14 +00:00
NVPTX [NVPTX] Fix sign/zero-extending ldg/ldu instruction selection 2016-05-02 18:12:02 +00:00
PowerPC [PowerPC] Add a testcase for TCO on string rvo function 2016-05-20 22:42:01 +00:00
SPARC [Sparc] Enable more inline assembly constraints. 2016-05-20 09:03:01 +00:00
SystemZ [SystemZ] Fix register ordering for BinaryRRF instructions 2016-05-18 13:24:57 +00:00
Thumb ARM: stop emitting blx instructions for most calls on MachO. 2016-05-10 19:17:47 +00:00
Thumb2 ARM: stop emitting blx instructions for most calls on MachO. 2016-05-10 19:17:47 +00:00
WebAssembly [WebAssembly] Make several CHECK lines less fragile using regexes and CHECK-DAG. 2016-05-19 01:52:56 +00:00
WinEH [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
X86 [X86][AVX] Generalized matching for target shuffle combines 2016-05-20 16:19:30 +00:00
XCore [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00