fed83adbe3
Teach tblgen to accept register source operands in patterns, e.g.
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def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src),
"shl{b} {%cl, $dst|$dst, %CL}",
[(set R8:$dst, (shl R8:$src, CL))]>, Imp<[CL],[]>;
This generates a CopyToReg operand and added its 2nd result to the shl as
a flag operand.
llvm-svn: 24557
2005-12-01 00:18:45 +00:00
faad542d24
Nuke CodeGenInstruction's ValueType member, it is no longer used.
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llvm-svn: 24556
2005-12-01 00:12:04 +00:00
cdf2c67888
Stop checking the ValueType of the CodeGenInstruction. Instead, use the
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ValueType from the RegisterClass or Operands. This step is necessary to
allow RegisterClasses to have multiple ValueTypes.
llvm-svn: 24555
2005-12-01 00:06:14 +00:00
e479ccb27b
fit into 80 columns
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llvm-svn: 24554
2005-11-30 23:58:18 +00:00
3e63dc00da
Make the code generated by tblgen return the result of SelectNodeTo, to
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permit future changes.
llvm-svn: 24553
2005-11-30 23:08:45 +00:00
4b25924d2a
SelectNodeTo now returns its result, we must pay attention to it.
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llvm-svn: 24552
2005-11-30 23:04:38 +00:00
a75694aa16
Pay attn to the node returned by SelectNodeTo
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llvm-svn: 24551
2005-11-30 23:02:08 +00:00
af2e0373dd
SelectNodeTo now returns its result, we must pay attention to it.
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llvm-svn: 24550
2005-11-30 22:59:19 +00:00
e318977940
SelectNodeTo now returns N. Use it instead of return N directly.
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llvm-svn: 24549
2005-11-30 22:53:06 +00:00
be5dd5da19
Make SelectNodeTo return N
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llvm-svn: 24548
2005-11-30 22:45:14 +00:00
3713e6b49c
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
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llvm-svn: 24547
2005-11-30 20:40:54 +00:00
bd065599e6
Test that crashes the ppc backend.
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llvm-svn: 24546
2005-11-30 20:40:28 +00:00
dc4ffef633
Fix a bug where we didn't realize that vaarg reads memory. This fixes
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Transforms/DeadStoreElimination/2005-11-30-vaarg.ll
llvm-svn: 24545
2005-11-30 19:38:22 +00:00
6299905a06
new testcase dse is miscompiling
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llvm-svn: 24544
2005-11-30 19:37:08 +00:00
fb619ef95c
Add a simple clear() method
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llvm-svn: 24543
2005-11-30 19:31:23 +00:00
11695c0537
Fix a typo in my latest change
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llvm-svn: 24542
2005-11-30 18:57:39 +00:00
6f8c1ace6e
No longer track value types for asm printer operands, and remove them as
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an argument to every operand printing function. Requires some slight
tweaks to x86, the only user.
llvm-svn: 24541
2005-11-30 18:54:35 +00:00
f621b333f3
Fix some copy and paste typos.
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llvm-svn: 24540
2005-11-30 18:37:14 +00:00
c174048430
CALLSEQ_START/END nodes don't get memoized, do not add them in when
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replaceAllUses'ing.
llvm-svn: 24539
2005-11-30 18:20:52 +00:00
7ffe3affda
remove redundant code
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llvm-svn: 24538
2005-11-30 17:14:11 +00:00
6ee8566cae
At long last, you can say that f32 isn't supported for setcc
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llvm-svn: 24537
2005-11-30 17:12:26 +00:00
ede966e8ee
Make typesafe that which isn't: FCMOVxx
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llvm-svn: 24536
2005-11-30 17:11:20 +00:00
873ed82a36
FPSelect and more custom lowering
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llvm-svn: 24535
2005-11-30 16:10:29 +00:00
1064d6ec43
First chunk of actually generating vector code for packed types. These
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changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
llvm-svn: 24534
2005-11-30 08:22:07 +00:00
6db615df14
All sorts of stuff.
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Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy. They should be custom lowered though.
Lots more stuff compiles now (go go single source!). Of course, none of it
probably works, but that is what the nightly tester can find out :)
llvm-svn: 24533
2005-11-30 07:19:56 +00:00
8d17c70171
add support for custom lowering SINT_TO_FP
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llvm-svn: 24531
2005-11-30 06:43:03 +00:00
b2d8f04437
Add a link to the doxygen tarball
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llvm-svn: 24530
2005-11-30 06:35:34 +00:00
0f6342f669
copy the doxygen tarball into the HTML directory after building it
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llvm-svn: 24529
2005-11-30 06:31:28 +00:00
893a45b86a
minor cleanup
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llvm-svn: 24528
2005-11-30 05:26:03 +00:00
3fd1b4c9bf
Fix a problem with llvm-ranlib that (on some platforms) caused the archive
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file to become corrupted due to interactions between mmap'd memory segments
and file descriptors closing. The problem is completely avoiding by using
a third temporary file.
Patch provided by Evan Jones
llvm-svn: 24527
2005-11-30 05:21:10 +00:00
9c7af08bc9
Fix a bug in a recent patch that broke shifts
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llvm-svn: 24526
2005-11-30 05:11:18 +00:00
4eb7af9bc9
Added support to STORE and shifts to DAG to DAG isel.
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llvm-svn: 24525
2005-11-30 02:51:20 +00:00
11d61613af
Fixed a bug introduced by my last commit: TargetGlobalValues should key on
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GlobalValue * and index pair. Update getGlobalAddress() for symmetry.
llvm-svn: 24524
2005-11-30 02:49:21 +00:00
0e0de2f3f0
Added an index field to GlobalAddressSDNode so it can represent X+12, etc.
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llvm-svn: 24523
2005-11-30 02:04:11 +00:00
d2cb70513d
Fixed a minor bug: - -offset != offset iff offset == MININT
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llvm-svn: 24522
2005-11-30 01:59:00 +00:00
048b26387b
Represent the encoding of the SPR instructions as they actually are, so
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that we can use the correct SPR numbers in the InstrInfo.td file. This is
necessary to support VRsave.
llvm-svn: 24521
2005-11-29 22:42:50 +00:00
72ab335858
Add more X86 ISel patterns.
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llvm-svn: 24520
2005-11-29 19:38:52 +00:00
c8af0cb893
Better error message when unrecognized opcode is seen.
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llvm-svn: 24519
2005-11-29 18:44:58 +00:00
3e7db9c6d5
Hook up one type, v4f32, to the VR RegisterClass for now.
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llvm-svn: 24517
2005-11-29 08:17:20 +00:00
c138118cdb
Add the remainder of the AltiVec 4 x float instructions. Further
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enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.
llvm-svn: 24516
2005-11-29 08:04:45 +00:00
435b402e1f
Add support for a new STRING and LOCATION node for line number support, patch
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contributed by Daniel Berlin, with a few cleanups here and there by me.
llvm-svn: 24515
2005-11-29 06:21:05 +00:00
4d0251ad55
Add the new vector types to tablegen
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llvm-svn: 24514
2005-11-29 06:19:38 +00:00
9c415364cf
No targets support line number info yet.
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llvm-svn: 24513
2005-11-29 06:16:21 +00:00
5a8726c575
Add support for a new STRING and LOCATION node for line number support, patch
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contributed by Daniel Berlin, with a few cleanups here and there by me.
llvm-svn: 24512
2005-11-29 06:15:39 +00:00
89b049af90
Add the majority of the vector machien value types we expect to support,
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and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
1d4af53444
Fixed a comment bug:
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createPPCPatternInstructionSelector -> createPPCISelPattern
llvm-svn: 24510
2005-11-29 04:59:46 +00:00
a31983137a
Add "SCC" to the lexicon. Patch provided by Marco Matthies, thanks!
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llvm-svn: 24509
2005-11-29 01:34:50 +00:00
45edf8a27d
Fix PR670 and test/Regression/Transforms/Mem2Reg/2005-11-28-Crash.ll
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llvm-svn: 24508
2005-11-29 01:07:12 +00:00
7cc680ab79
new testcase for pr670
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llvm-svn: 24507
2005-11-29 01:06:51 +00:00
d8bc778352
add Evan and Jim. Please edit your entries as desired.
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llvm-svn: 24506
2005-11-29 00:57:06 +00:00
Evan Cheng