Commit Graph

53500 Commits

Author SHA1 Message Date
Kostya Serebryany 84a7f2e8e9 [asan] fix one more bug related to long double
llvm-svn: 153189
2012-03-21 15:28:50 +00:00
Joerg Sonnenberger a29b5bd2a8 Put Is64BitMemOperand into !defined(NDEBUG) for now.
llvm-svn: 153185
2012-03-21 14:09:26 +00:00
Benjamin Kramer bc1066734f Use a signed value for this enum to avoid spuriuos warnings from gcc.
llvm-svn: 153184
2012-03-21 13:48:11 +00:00
Chandler Carruth 3ffccb3802 Teach instsimplify to gracefully degrade in the presence of instructions
not attched to a basic block or function. There are conservatively
correct answers in these cases, and this makes the analysis more useful
in contexts where we have a partially formed bit of IR.

I don't have any way to test this directly... suggestions welcome here,
but I'm not seeing anything sadly. I only found this using a subsequent
patch to the inliner which runs instsimplify on partially inlined
instructions, and even then only on a quite large program. I never got
a reasonable testcase out of it, and anything I do get is likely to be
quite fragile due to requiring an interaction of two different passes,
and the only result being a segfault if it goes wrong.

llvm-svn: 153176
2012-03-21 10:58:47 +00:00
Joerg Sonnenberger 5463e66768 Fix generation of the address size override prefix. Add assertions for
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.

llvm-svn: 153166
2012-03-21 05:48:07 +00:00
Andrew Trick 25baeca54d misched: fix LiveInterval update for bottom-up scheduling
llvm-svn: 153162
2012-03-21 04:12:16 +00:00
Andrew Trick adb03b91ee misched: trace LiveIntervals after scheduling.
llvm-svn: 153161
2012-03-21 04:12:12 +00:00
Andrew Trick 54f7def703 misched: obvious iterator update fixes for bottom-up.
llvm-svn: 153160
2012-03-21 04:12:10 +00:00
Andrew Trick de670c0304 misched: cleanup main loop
llvm-svn: 153159
2012-03-21 04:12:07 +00:00
Andrew Trick 3bfafcba10 misched: fix LI update for bottom-up.
llvm-svn: 153158
2012-03-21 04:12:01 +00:00
Craig Topper 344e0128ba Add typecast to silence -Wswitch warning introduced by r153153.
llvm-svn: 153155
2012-03-21 02:28:53 +00:00
Craig Topper 9cfc69c779 Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend.
llvm-svn: 153154
2012-03-21 02:14:01 +00:00
Akira Hatanaka 0137dfe42a Incremental big endian patch by Jack Carter.
These changes allow us to compile big endian from the command line for 32 bit
Mips targets. This patch will result in code and data actually being produced
in the correct endianess.

llvm-svn: 153153
2012-03-21 00:52:01 +00:00
Eric Christopher 7d522f161d Zap some dead code pointed out by Chandler.
llvm-svn: 153150
2012-03-20 23:28:58 +00:00
Sean Callanan eba3a66055 RuntimeDyldMachO has the ability to keep track of
relocations (i.e., pieces of data whose addresses
are referred to elsewhere in the binary image) and
update the references when the section containing
the relocations moves.  The way this works is that
there is a map from section IDs to lists of
relocations.

Because the relocations are associated with the
section containing the data being referred to, they
are updated only when the target moves.  However,
many data references are relative and also depend
on the location of the referrer.

To solve this problem, I introduced a new data
structure, Referrer, which simply contains the
section being referred to and the index of the
relocation in that section.  These referrers are
associated with the source containing the
reference that needs to be updated, so now
regardless of which end of the relocation moves,
the relocation will now be updated correctly.

llvm-svn: 153147
2012-03-20 22:25:39 +00:00
Chad Rosier 4106917355 [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to
vextractf128 with 128-bit mem dest.

Combines

	vextractf128 $0, %ymm0, %xmm0
	vmovaps %xmm0, (%rdi)

to

    vextractf128 $0, %ymm0, (%rdi)

rdar://11082570

llvm-svn: 153139
2012-03-20 21:43:40 +00:00
Jim Grosbach 1283317db4 Assembler should accept redefinitions of unused variable symbols.
rdar://11027851

llvm-svn: 153137
2012-03-20 21:33:21 +00:00
Jim Grosbach 765a6e0231 Tidy up.
llvm-svn: 153136
2012-03-20 21:33:17 +00:00
Evan Cheng 759b1d169f Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand.
llvm-svn: 153135
2012-03-20 21:28:05 +00:00
Andrew Trick f7711010e1 LoopSimplify bug fix. Handle indirect loop back edges.
Do not call SplitBlockPredecessors on a loop preheader when one of the
predecessors is an indirectbr. Otherwise, you will hit this assert:
!isa<IndirectBrInst>(Preds[i]->getTerminator()) && "Cannot split an edge from an IndirectBrInst"

llvm-svn: 153134
2012-03-20 21:24:52 +00:00
Andrew Trick bb01cbb312 whitespace
llvm-svn: 153133
2012-03-20 21:24:47 +00:00
Andrew Trick 9c45706baf LSR: teach isSimplifiedLoopNest to handle PHI IVUsers.
llvm-svn: 153132
2012-03-20 21:24:44 +00:00
Andrew Trick 3660735e18 LSR: fix IVUsers isSimplifiedLoopNest to perform a full domtree walk
instead of skipping the current loop.

My prior fix was incomplete because of an overzealous compile-time optimization:
Better fix for: <rdar://problem/11049788> Segmentation fault: 11 in LoopStrengthReduce

llvm-svn: 153131
2012-03-20 21:24:40 +00:00
Matt Beaumont-Gay dc873d5e6a remove unused variable
llvm-svn: 153116
2012-03-20 19:52:05 +00:00
Chad Rosier 0158ae2e5b [avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give
precedence over the VINSERTF128 avx1 patterns.

llvm-svn: 153114
2012-03-20 19:45:07 +00:00
Bob Wilson b60f8f875c Require a base pointer for stack realignment when SP may vary dynamically.
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls.  Use hasReservedCallFrame() to
check for both.  The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.

<rdar://problem/11075906>

llvm-svn: 153110
2012-03-20 19:28:25 +00:00
Bob Wilson ca690320fb Remove some redundant checks.
ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.

llvm-svn: 153109
2012-03-20 19:28:22 +00:00
Chad Rosier 93d5427c69 Whitespace.
llvm-svn: 153105
2012-03-20 18:38:33 +00:00
Chad Rosier 5a6011267a [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove
whitespace from test case.  No functional change intended.

llvm-svn: 153103
2012-03-20 18:24:55 +00:00
Kevin Enderby 816ca27ef6 Fix assembling ARM vst2 instructions with double-spaced registers.
llvm-svn: 153099
2012-03-20 17:41:51 +00:00
Jim Grosbach 997614f597 ARM non-scattered MachO relocations for movw/movt.
Needed when building -mdynamic-no-pic code.

rdar://10459256

llvm-svn: 153097
2012-03-20 17:25:45 +00:00
Chad Rosier 07a4cb9382 [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.
This results in things such as

	vmovups	16(%rdi), %xmm0
	vinsertf128	$1, %xmm0, %ymm0, %ymm0

to be combined to

    vinsertf128	$1, 16(%rdi), %ymm0, %ymm0

rdar://11076953

llvm-svn: 153092
2012-03-20 17:08:51 +00:00
Silviu Baranga 32a49333ec The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
llvm-svn: 153089
2012-03-20 15:54:56 +00:00
Richard Barton 7caea33dfa Test Commit - add a newline
llvm-svn: 153083
2012-03-20 10:50:35 +00:00
Bill Wendling 7315c4b9cd It's possible to have a constant expression who's size is quite big (e.g.,
i128). In that case, we may not be able to print out the MCExpr as an
expression. For instance, we could have an MCExpr like this:

    0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64)

The MCExpr printer handles sizes up to 64-bits, but this expression would
require 128-bits. In this situation, try to evaluate the constant expression and
emit that as the value into 64-bit chunks.
<rdar://problem/11070338>

llvm-svn: 153081
2012-03-20 08:56:43 +00:00
Craig Topper b34d96c614 Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met.
llvm-svn: 153080
2012-03-20 07:17:59 +00:00
Craig Topper cbc96a6e90 Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change.
llvm-svn: 153079
2012-03-20 06:42:26 +00:00
Craig Topper aaeae98936 When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend.
llvm-svn: 153078
2012-03-20 05:28:39 +00:00
Eric Christopher 60e01c560a Do everything up to generating code to try to get a register for
a variable. The previous code would break the debug info changing
code invariant. This will regress debug info for arguments where
we elide the alloca created.

Fixes rdar://11066468

llvm-svn: 153074
2012-03-20 01:07:58 +00:00
Eric Christopher 997aaa9237 Untabify.
llvm-svn: 153073
2012-03-20 01:07:56 +00:00
Eric Christopher e5e54c87fa Add another debugging statement here.
llvm-svn: 153072
2012-03-20 01:07:53 +00:00
Eric Christopher 1a06cc9ae6 Use lookUpRegForValue here instead of duplicating the code.
llvm-svn: 153071
2012-03-20 01:07:47 +00:00
Pete Cooper e69be6df4f f16 FDIV can now be legalized by promoting to f32
llvm-svn: 153064
2012-03-19 23:38:12 +00:00
Chris Lattner 8c3c65067d fix a build failure with libc++
llvm-svn: 153063
2012-03-19 23:31:01 +00:00
Jim Grosbach c4aa60ffe9 ARM branch relaxation for unconditional t1 branches.
rdar://11059157

llvm-svn: 153055
2012-03-19 21:32:32 +00:00
Jim Grosbach 67e76babd3 ARM assembly, accept optional '#' on lane index number.
rdar://11057160

llvm-svn: 153053
2012-03-19 20:39:53 +00:00
Michael J. Spencer 9da9e6937f [Object/COFF]: Expose getSectionContents.
llvm-svn: 153051
2012-03-19 20:27:37 +00:00
Michael J. Spencer 53c2d5477a [Object/COFF]: Expose getSectionName.
Also add some documentation.

llvm-svn: 153050
2012-03-19 20:27:15 +00:00
Anton Korobeynikov 3edd854d64 Perform mul combine when multiplying wiht negative constants.
Patch by Weiming Zhao!
This fixes PR12212

llvm-svn: 153049
2012-03-19 19:19:50 +00:00
Lang Hames dd98c497b9 Add an option to the MI scheduler to cut off scheduling after a fixed number of
instructions have been scheduled. Handy for tracking down scheduler bugs, or
bugs exposed by scheduling.

llvm-svn: 153045
2012-03-19 18:38:38 +00:00