Commit Graph

9 Commits

Author SHA1 Message Date
Tom Stellard 0ebf29d41f Revert "TableGen: Enumerate Schedule Model too."
This reverts commit 2ca1e4a39c7e0d7a00e66ff5437c6d7ace2404a0.

llvm-svn: 187525
2013-07-31 20:43:08 +00:00
Vincent Lejeune 22e6ddd475 TableGen: Enumerate Schedule Model too.
llvm-svn: 187511
2013-07-31 19:31:20 +00:00
Sean Silva d01eead98c [docs] Amend confusing title
"Writing an LLVM Compiler Backend" can be misinterpreted as meaning
"backend" in the sense of "using LLVM as a backend for your compiler for
your new language". This new name is less ambiguous.

As a bonus, this brings the title in line with the file name.

llvm-svn: 185377
2013-07-01 20:45:12 +00:00
Tom Stellard b162d94871 TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.

In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.

For example, if you have an instruction like:

def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;

You can look up the operand indices using the new function, like this:

Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst)  => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2

The operand names are case sensitive, so $dst and $DST are considered
different operands.

This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values.  These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.

llvm-svn: 184879
2013-06-25 21:22:09 +00:00
Jakob Stoklund Olesen 83aa671f09 Give Sparc instruction patterns direct types instead of register classes.
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.

llvm-svn: 177835
2013-03-24 00:56:20 +00:00
Chris Lattner 045a73e62d remove the rest of the "written by" lines in the documentation. It is
against the developer policy to include this sort of thing as SVN blame
already captures this in a far more fine-grained way.

llvm-svn: 172109
2013-01-10 21:24:04 +00:00
Sean Silva 6e4ebb5424 docs: Fix FIXME
I actually made a think-o when writing this FIXME since I wrote LangRef
but it should actually have said WritingAnLLVMBackend.

llvm-svn: 171293
2012-12-31 11:49:51 +00:00
Dmitri Gribenko 11ffe2c47e Documentation: convert WritingAnLLVMPass.html to reST.
Patch by Anthony Mykhailenko with small fixes by me.

llvm-svn: 169992
2012-12-12 17:02:44 +00:00
Dmitri Gribenko 7174c5a074 Documentation: convert WritingAnLLVMBackend.html to reST
llvm-svn: 169087
2012-12-01 12:13:48 +00:00