Commit Graph

164 Commits

Author SHA1 Message Date
Bill Wendling 3d7b0b8ac7 Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.
llvm-svn: 170502
2012-12-19 07:18:57 +00:00
Jyotsna Verma 92e71918b1 Use multiclass for new-value store instructions with MEMri operand.
llvm-svn: 169814
2012-12-11 05:12:25 +00:00
NAKAMURA Takumi 6b819c5fb1 [CMake] Update dependencies to intrinsics_gen corresponding to r169711.
llvm-svn: 169724
2012-12-10 05:27:15 +00:00
Matthew Curtis 7a93811e8b In hexagon convertToHardwareLoop, don't deref end() iterator
In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html

llvm-svn: 169634
2012-12-07 21:03:15 +00:00
Jyotsna Verma d3746e6895 Define new-value store instructions with base+immediate addressing mode
using multiclass.

llvm-svn: 169432
2012-12-05 22:02:56 +00:00
Jyotsna Verma 90295156d8 Use multiclass to define store instructions with base+immediate offset
addressing mode and immediate stored value.

llvm-svn: 169408
2012-12-05 19:32:03 +00:00
Matthew Curtis cd8c881c9f Fix misplaced closing brace.
llvm-svn: 169404
2012-12-05 19:00:34 +00:00
Jyotsna Verma 4da904c8f8 Define store instructions with base+register offset addressing mode
using multiclass.

llvm-svn: 169314
2012-12-04 21:58:25 +00:00
Jyotsna Verma dfd779e108 Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros)
instructions.

llvm-svn: 169287
2012-12-04 18:05:01 +00:00
Jyotsna Verma 22d61dd4ce Add constant extender support to ALU32 instructions for V2.
llvm-svn: 169284
2012-12-04 17:12:00 +00:00
Chandler Carruth 802d755533 Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224
2012-12-04 07:12:27 +00:00
Jyotsna Verma 5929cfc534 Move all operand definitions into HexagonOperands.td
llvm-svn: 169213
2012-12-04 05:00:31 +00:00
Jyotsna Verma efe4f559b1 Move generic Hexagon subtarget information into Hexagon.td
llvm-svn: 169212
2012-12-04 04:29:16 +00:00
Jyotsna Verma 6f3bd03e50 Define store instructions with base+immediate offset addressing mode
using multiclass.

llvm-svn: 169168
2012-12-03 22:26:28 +00:00
Jyotsna Verma 4d8686cc42 Define load instructions with base+immediate offset addressing mode
using multiclass.

llvm-svn: 169153
2012-12-03 21:13:13 +00:00
Jyotsna Verma c86b3e1b26 Define unsigned const-ext predicates.
llvm-svn: 169149
2012-12-03 20:39:45 +00:00
Jyotsna Verma 6aba56e9d4 Removing unnecessary 'else' statement from the predicates defined in HexagonOperards.td.
llvm-svn: 169148
2012-12-03 20:14:38 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Jyotsna Verma 014dfe4de0 Define signed const-ext predicates.
llvm-svn: 169117
2012-12-03 06:54:50 +00:00
Jyotsna Verma a77c054e85 Use multiclass for the load instructions with MEMri operand.
llvm-svn: 169018
2012-11-30 17:31:52 +00:00
Jyotsna Verma b950ea61fc Use multiclass for the store instructions with MEMri operand.
llvm-svn: 168983
2012-11-30 06:10:22 +00:00
Jyotsna Verma ede608cce0 Use multiclass for the load instructions with 'base + register offset'
addressing mode.

llvm-svn: 168976
2012-11-30 04:19:09 +00:00
Jyotsna Verma e95559fc16 Use multiclass for 'transfer' instructions.
llvm-svn: 168929
2012-11-29 19:35:44 +00:00
Jyotsna Verma 519b3856dd Define signed const-ext immediate operands and their predicates.
llvm-svn: 168810
2012-11-28 20:58:14 +00:00
Jyotsna Verma b5bb659d50 Fix comments in HexagonOperands.td.
llvm-svn: 168617
2012-11-26 21:56:51 +00:00
Jyotsna Verma 0df99bd2e4 Add new predicates for the immediate operands.
llvm-svn: 168451
2012-11-21 20:05:09 +00:00
Jyotsna Verma 3ec3a49432 Use one common 'let' expression to set PrintMethod for all immediate operands.
llvm-svn: 168449
2012-11-21 19:53:42 +00:00
Rafael Espindola b90c5f12f0 Finish the renaming.
llvm-svn: 168437
2012-11-21 16:56:33 +00:00
Jyotsna Verma 6c0a3550c8 Renamed HexagonImmediates.td -> HexagonOperands.td.
llvm-svn: 168434
2012-11-21 16:28:18 +00:00
Jyotsna Verma c6f2465b5d Removing some unused instruction definitions from the Hexagon backend.
llvm-svn: 168388
2012-11-20 22:14:23 +00:00
Jyotsna Verma 6649360860 Added multiclass for post-increment load instructions.
llvm-svn: 167974
2012-11-14 20:38:48 +00:00
Jyotsna Verma ccfd77ef90 Test commit.
Add a blank line.

llvm-svn: 167819
2012-11-13 06:31:55 +00:00
Andrew Trick baeaabb2d0 ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.

llvm-svn: 167435
2012-11-06 03:13:46 +00:00
Pranav Bhandarkar 34b601804e Use the relationship models infrastructure to add two relations - getPredOpcode
and getPredNewOpcode. The first relates non predicated instructions with their
predicated forms and the second relates predicated instructions with their
predicate-new forms.

Patch by Jyotsna Verma!

llvm-svn: 167243
2012-11-01 19:13:23 +00:00
Nadav Rotem 2289f2c932 Implement a basic VectorTargetTransformInfo interface to be used by the loop and bb vectorizers for modeling the cost of instructions.
llvm-svn: 166593
2012-10-24 17:22:41 +00:00
Nadav Rotem 5dc203e8f4 Reapply the TargerTransformInfo changes, minus the changes to LSR and Lowerinvoke.
llvm-svn: 166248
2012-10-18 23:22:48 +00:00
Bob Wilson d6d9ccca38 Temporarily revert the TargetTransform changes.
The TargetTransform changes are breaking LTO bootstraps of clang.  I am
working with Nadav to figure out the problem, but I am reverting it for now
to get our buildbots working.

This reverts svn commits: 165665 165669 165670 165786 165787 165997
and I have also reverted clang svn 165741

llvm-svn: 166168
2012-10-18 05:43:52 +00:00
Nadav Rotem e10328737d Add a new interface to allow IR-level passes to access codegen-specific information.
llvm-svn: 165665
2012-10-10 22:04:55 +00:00
Andrew Trick dd79f0fcea misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

llvm-svn: 165603
2012-10-10 05:43:09 +00:00
Bill Wendling c9b22d735a Create enums for the different attributes.
We use the enums to query whether an Attributes object has that attribute. The
opaque layer is responsible for knowing where that specific attribute is stored.

llvm-svn: 165488
2012-10-09 07:45:08 +00:00
Micah Villmow cdfe20b97f Move TargetData to DataLayout.
llvm-svn: 165402
2012-10-08 16:38:25 +00:00
Bill Wendling b0a290ef9e Use new accessor methods to query for attributes.
llvm-svn: 165205
2012-10-04 06:43:21 +00:00
Sebastian Pop edb31faf92 TargetLowering interface to set/get minimum block entries for jump tables.
Provide interface in TargetLowering to set or get the minimum number of basic
blocks whereby jump tables are generated for switch statements rather than an
if sequence.

    getMinimumJumpTableEntries() defaults to 4.
    setMinimumJumpTableEntries() allows target configuration.

    This patch changes the default for the Hexagon architecture to 5
    as it improves performance on some benchmarks.

llvm-svn: 164628
2012-09-25 20:35:36 +00:00
Sergei Larin 2db64a7031 DAG post-process for Hexagon MI scheduler
This patch introduces a possibility for Hexagon MI scheduler
to perform some target specific post- processing on the scheduling
DAG prior to scheduling.

llvm-svn: 163903
2012-09-14 15:07:59 +00:00
Benjamin Kramer 61f6708eee Remove redundant private field.
clang warned about this being unused in Release builds.

llvm-svn: 163899
2012-09-14 12:19:58 +00:00
Andrew Trick 7a8e10042f Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

llvm-svn: 163580
2012-09-11 00:39:15 +00:00
Sergei Larin ef4cc11cf9 Add "blocked" heuristic to the Hexagon MI scheduler.
Improve AQ instruction selection in the Hexagon MI scheduler.

llvm-svn: 163523
2012-09-10 17:31:34 +00:00
Benjamin Kramer 68b9f0583f Fix alignment of .comm and .lcomm on mingw32.
For some reason .lcomm uses byte alignment and .comm log2 alignment so we can't
use the same setting for both. Fix this by reintroducing the LCOMM enum.
I verified this against mingw's gcc.

llvm-svn: 163420
2012-09-07 21:08:01 +00:00
Benjamin Kramer 47f9ec92cb MC: Overhaul handling of .lcomm
- Darwin lied about not supporting .lcomm and turned it into zerofill in the
  asm parser. Push the zerofill-conversion down into macho-specific code.
- This makes the tri-state LCOMMType enum superfluous, there are no targets
  without .lcomm.
- Do proper error reporting when trying to use .lcomm with alignment on a target
  that doesn't support it.
- .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2.
- Fixes PR13755 (.lcomm crashes on ELF).

llvm-svn: 163395
2012-09-07 17:25:13 +00:00
Pranav Bhandarkar 823f9ebaa3 LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the
subreg_hireg of register pair Rp.

	* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
	 DenseMap similar to PeepholeMap that additionally records subreg info
	 too.
        (runOnMachineFunction): Record information in PeepholeDoubleRegsMap
        and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
	the instruction Rx = COPY Rp1:logreg_subreg.
	* test/CodeGen/Hexagon/remove_lsr.ll: New test.
	

llvm-svn: 163214
2012-09-05 16:01:40 +00:00