d1822ea7d1
Move lengthy conditional down 1 level per review comment.
...
llvm-svn: 40878
2007-08-06 21:48:35 +00:00
75169a82d6
Get X86 long double calling convention to work
...
(on Darwin, anyway). Fix some table omissions for
LD arithmetic.
llvm-svn: 40877
2007-08-06 21:31:06 +00:00
e279fd6ce8
Make 80-bit store maintain simulated FP stack correctly.
...
llvm-svn: 40868
2007-08-06 19:50:32 +00:00
446282ae3d
Fix minor doxygen nits.
...
llvm-svn: 40854
2007-08-05 20:06:04 +00:00
b1888e73ad
Long double patch 4 of N: initial x87 implementation.
...
Lots of problems yet but some simple things work.
llvm-svn: 40847
2007-08-05 18:49:15 +00:00
7132e00de7
This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.
...
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.
llvm-svn: 40807
2007-08-04 01:51:18 +00:00
b0c7585f2d
Make x86 long double alignment 32 for everything but
...
Darwin (which makes size within a struct==96)
llvm-svn: 40796
2007-08-03 22:46:15 +00:00
c5283ecd6f
long double patch 2 of N. Handle it in TargetData.
...
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)
llvm-svn: 40792
2007-08-03 20:20:50 +00:00
99fbf13dc3
add an observation
...
llvm-svn: 40772
2007-08-03 00:17:42 +00:00
5f6a9da530
More explicit keywords.
...
llvm-svn: 40757
2007-08-02 21:21:54 +00:00
8932bff7fe
Fix the alignment requirements of several unpck and shuf instructions.
...
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.
llvm-svn: 40756
2007-08-02 21:17:01 +00:00
4d436e2b7d
Fix pastos in vector arithmetic intrinsics.
...
llvm-svn: 40754
2007-08-02 21:06:40 +00:00
fa3eeeedc0
Mark the SSE and MMX load instructions that
...
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.
llvm-svn: 40736
2007-08-02 14:27:55 +00:00
473c5111c3
Switch some multiplication instructions over to the new scheme for testing.
...
llvm-svn: 40723
2007-08-02 05:48:35 +00:00
d3d92890fc
Can't handle offset and scale if rip-relative addressing is to be used.
...
llvm-svn: 40703
2007-08-01 23:46:47 +00:00
9a3b2b09ad
Mac OS X X86-64 low 4G address not available.
...
llvm-svn: 40702
2007-08-01 23:46:10 +00:00
763cdfd371
Mac OS X X86-64 low 4G address not available.
...
llvm-svn: 40701
2007-08-01 23:45:51 +00:00
58c3c30921
Some out operands were incorrectly specified as input operands.
...
llvm-svn: 40697
2007-08-01 23:07:38 +00:00
da549ece5c
Missing Requires.
...
llvm-svn: 40691
2007-08-01 21:42:24 +00:00
6f2ce6b842
Be more precise.
...
llvm-svn: 40689
2007-08-01 20:22:37 +00:00
d541c831c3
Change a .size directive to use a tab instead of a space, for consistency.
...
llvm-svn: 40672
2007-08-01 14:42:30 +00:00
aa39b39eec
Indexed loads each has 2 outputs.
...
llvm-svn: 40658
2007-08-01 00:12:08 +00:00
54ec4bfa5f
Change the x86 assembly output to use tab characters to separate the
...
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.
llvm-svn: 40648
2007-07-31 20:11:57 +00:00
12c6be84ff
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
...
llvm-svn: 40628
2007-07-31 08:04:03 +00:00
242a87734a
This isn't safe when there are uses of load's chain result.
...
llvm-svn: 40617
2007-07-31 06:21:44 +00:00
204dece054
Use tabs more consistently in assembler pseudo-ops.
...
llvm-svn: 40594
2007-07-30 15:08:02 +00:00
55360dacd4
Fix the comment for getClosestTargetForJIT to reflect the fact that
...
it does not have a Module parameter.
llvm-svn: 40590
2007-07-30 14:58:59 +00:00
e379f08b19
More explicit keywords.
...
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
581d2795dc
Vector fneg must be expanded into fsub -0.0, X.
...
llvm-svn: 40586
2007-07-30 07:51:22 +00:00
5fecb80efa
Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
...
llvm-svn: 40578
2007-07-29 01:24:57 +00:00
ac3a364c51
Add register info needed to use subreg sets on X86.
...
llvm-svn: 40572
2007-07-28 19:03:30 +00:00
ce38853cc6
Trampoline codegen support for X86-32.
...
llvm-svn: 40566
2007-07-27 20:02:49 +00:00
4788552deb
Re-apply 40504, but with a fix for the segfault it caused in oggenc:
...
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.
llvm-svn: 40555
2007-07-27 17:16:43 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
...
still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
931de40afa
Reverting 40504 for now. It's breaking oggenc.
...
llvm-svn: 40547
2007-07-27 01:37:47 +00:00
d204d08b97
Make sure epilogue esp adjustment is placed before any terminator and pop instructions.
...
llvm-svn: 40538
2007-07-26 17:45:41 +00:00
936d17aa1b
Don't pollute the meaning of isUnpredicatedTerminator.
...
llvm-svn: 40537
2007-07-26 17:32:14 +00:00
ca6e041903
Minor bug.
...
llvm-svn: 40535
2007-07-26 17:02:45 +00:00
c9edd977ea
In the .loc directive, print the fields as "debug" fields, so they
...
don't get decorated as if for immediate fields for instructions.
llvm-svn: 40529
2007-07-26 15:24:15 +00:00
cecd4b3793
Fix a whitespace difference between CMPSSrr and CMPSDrr.
...
llvm-svn: 40528
2007-07-26 15:11:50 +00:00
cde0ee5221
Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
...
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
ce5185b181
Same goes for constantpool, etc.
...
llvm-svn: 40517
2007-07-26 07:35:15 +00:00
a8fc0e527b
Add selection DAG nodes for subreg insert/extract. PR1350
...
llvm-svn: 40516
2007-07-26 07:34:40 +00:00
8455bd3fae
Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the
...
x86 target, replacing them with the new alignment attributes on memory
references.
llvm-svn: 40504
2007-07-26 00:31:09 +00:00
630c1f75b8
Mac OS X x86-64 lower 4G address is not available.
...
llvm-svn: 40502
2007-07-25 23:41:36 +00:00
952aa6988b
Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements.
...
llvm-svn: 40501
2007-07-25 23:36:05 +00:00
5c6a31e9a0
Functions with LinkOnce and weak linkage still need to be aligned. Doh.
...
llvm-svn: 40499
2007-07-25 22:28:16 +00:00
cf0a5349de
Don't ignore the return value of AsmPrinter::doInitialization and
...
AsmPrinter::doFinalization.
llvm-svn: 40487
2007-07-25 19:33:14 +00:00
5805c46e8f
Fix debug info and globals filled with zeros.
...
llvm-svn: 40483
2007-07-25 03:48:45 +00:00
64b64ae591
Minor cleanup:
...
- Split EH and debug infiormation
- Make DwarfWriter more verbose in some cases
llvm-svn: 40481
2007-07-25 00:06:28 +00:00
f0bb12848f
Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
...
llvm-svn: 40480
2007-07-24 23:00:27 +00:00
f906c7286f
Use movaps to load a v4f32 build_vector of all-constant values into a
...
register instead of loading each element individually.
llvm-svn: 40478
2007-07-24 22:55:08 +00:00
0c46451d2b
Heal EH handling stuff by emitting correct offsets to callee-saved registers.
...
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)
llvm-svn: 40472
2007-07-24 21:07:39 +00:00
b6a8ae20c7
Fix some uses of dyn_cast to be uses of cast.
...
llvm-svn: 40443
2007-07-23 20:24:29 +00:00
17f68f95d8
Delete the svn:executable property on these files, which aren't executable.
...
llvm-svn: 40441
2007-07-23 19:26:08 +00:00
3d88e9940a
Add missing SSE builtins:
...
__builtin_ia32_cvtss2si64
__builtin_ia32_cvttss2si64
__builtin_ia32_cvtsi642ss
__builtin_ia32_cvtsd2si64
__builtin_ia32_cvttsd2si64
__builtin_ia32_cvtsi642sd
llvm-svn: 40411
2007-07-23 03:07:27 +00:00
ac1591be42
No more noResults.
...
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
9d5df0a5f6
Added -print-emitted-asm to print out JIT generated asm to cerr.
...
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
8fefeffb37
Because we promote SSE logical ops and loads to v2i64, we often end up generate
...
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.
llvm-svn: 40076
2007-07-20 00:27:43 +00:00
9081ab8127
Oops. These stores actually produce results.
...
llvm-svn: 40074
2007-07-20 00:20:46 +00:00
64738536b3
Fix custom lowering of SSE FXOR.
...
llvm-svn: 40071
2007-07-19 23:36:01 +00:00
7ca3555bfa
Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)).
...
llvm-svn: 40070
2007-07-19 23:34:10 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
...
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
22b0c344db
Only adjust esp around calls in presence of alloca.
...
llvm-svn: 40030
2007-07-19 00:42:58 +00:00
7b5b06805a
Only adjust esp around calls in presence of alloca.
...
llvm-svn: 40028
2007-07-19 00:42:05 +00:00
8941071ae1
Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in.
...
llvm-svn: 40018
2007-07-18 21:26:06 +00:00
776962a97a
Implement initial memory alignment awareness for SSE instructions. Vector loads
...
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.
llvm-svn: 40015
2007-07-18 20:23:34 +00:00
f314055706
New entry.
...
llvm-svn: 39998
2007-07-18 08:21:49 +00:00
97b5dc63d7
Fold prologue esp update when possible.
...
llvm-svn: 39984
2007-07-17 21:26:42 +00:00
b2bb4b4040
Make sure not to break eh_return.
...
llvm-svn: 39978
2007-07-17 18:40:47 +00:00
27ba94bf3b
Update.
...
llvm-svn: 39977
2007-07-17 18:39:45 +00:00
67e2e22e97
Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan.
...
llvm-svn: 39974
2007-07-17 18:03:34 +00:00
9ae2eb43d8
Use push / pop for prologues and epilogues.
...
llvm-svn: 39967
2007-07-17 07:59:08 +00:00
396156e00b
no email addrs in file headers
...
llvm-svn: 39962
2007-07-17 05:56:43 +00:00
06c60b6032
Fix comments about vectors to use the current wording.
...
llvm-svn: 39921
2007-07-16 14:29:03 +00:00
383a324735
Long live the exception handling!
...
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
1fae1cd3e1
Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
...
llvm-svn: 39843
2007-07-13 23:55:50 +00:00
2182f06f2d
Skeleton of post-RA scheduler; doesn't do anything yet.
...
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.
llvm-svn: 39816
2007-07-13 17:13:54 +00:00
2b4d9b684f
Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551)
...
llvm-svn: 39813
2007-07-13 16:24:10 +00:00
85ee72f7ba
ARM: make branch folder remove unconditional branches
...
following jump tables that it earlier inserted. This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).
llvm-svn: 39782
2007-07-12 16:45:35 +00:00
bdc69595d9
another missed SSE optimization
...
llvm-svn: 39772
2007-07-12 06:31:38 +00:00
bcda5e20c9
Added support for Mips specific GAS directives
...
Fixed print immediate
Fixed Identation on MipsISelDAGToDAG.cpp
llvm-svn: 39764
2007-07-11 23:24:41 +00:00
6c8c748e4d
Added support for framepointer
...
Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!
llvm-svn: 39763
2007-07-11 23:21:31 +00:00
77dbdcabf2
Now that stack is represented the right way, LOA starts at 0
...
llvm-svn: 39761
2007-07-11 23:17:41 +00:00
4449e5dd7f
Fixed AddLiveOut issues
...
FI's created the write way to represent Mips stack
llvm-svn: 39760
2007-07-11 23:16:16 +00:00
c5affeccbd
Removed unused immediate PatLeaf, fixed lui instruction
...
llvm-svn: 39759
2007-07-11 22:47:02 +00:00
753e37027f
Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog
...
llvm-svn: 39758
2007-07-11 22:44:21 +00:00
3d70855dd2
Handle packed structs in the CBackend.
...
llvm-svn: 39752
2007-07-11 19:56:53 +00:00
e59411d056
Fix hang compiling TimberWolf (allow for islands
...
of size other than 4).
llvm-svn: 39743
2007-07-11 18:32:38 +00:00
09d73c0305
Assert when TLS is not implemented.
...
llvm-svn: 39737
2007-07-11 17:19:51 +00:00
6e544a9cca
Fix an oversight: for modules with no other identifying target info,
...
the sparc backend should be preferred when running on sparcs.
llvm-svn: 39142
2007-07-11 16:32:10 +00:00
94579dbd2e
Didn't mean the last commit. Revert.
...
llvm-svn: 38515
2007-07-10 22:00:16 +00:00
68471d263f
Fix fp_constant_op failure.
...
llvm-svn: 38514
2007-07-10 21:53:30 +00:00
effa7467b6
Update.
...
llvm-svn: 38513
2007-07-10 21:49:47 +00:00
23f631d87c
fix 80 columnn violations, increasing the world's
...
pedantic satisfaction level.
llvm-svn: 38512
2007-07-10 20:53:41 +00:00
f51bd666d9
add a note
...
llvm-svn: 38507
2007-07-10 20:03:50 +00:00
9d41b311fb
Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
...
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
0867337075
Remove clobbersPred.
...
llvm-svn: 38500
2007-07-10 18:07:08 +00:00
57111e7a60
Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp,
...
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.
llvm-svn: 38478
2007-07-10 00:05:58 +00:00
f8f531bf69
Change getCopyToParts and getCopyFromParts to always use target-endian
...
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.
llvm-svn: 38471
2007-07-09 20:59:04 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
...
zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
881248c4e1
No need for ccop anymore.
...
llvm-svn: 37965
2007-07-06 23:34:09 +00:00
3650b2c278
Incorrect check.
...
llvm-svn: 37962
2007-07-06 23:23:19 +00:00
76a97c5f8a
Do away with ImmutablePredicateOperand.
...
llvm-svn: 37961
2007-07-06 23:22:46 +00:00
d771e05121
isUnpredicatedTerminator should treat conditional branches as unpredicated terminator.
...
llvm-svn: 37960
2007-07-06 23:22:03 +00:00
b039c60889
Do away with ImmutablePredicateOperand.
...
llvm-svn: 37959
2007-07-06 23:21:02 +00:00
b567e3ffb0
Add the byval attribute
...
llvm-svn: 37940
2007-07-06 10:57:03 +00:00
0a42fdf346
Print the s bit if the instruction is toggled to its CPSR setting form.
...
llvm-svn: 37932
2007-07-06 01:01:34 +00:00
5c66888580
PredicateDefOperand -> OptionalDefOperand.
...
llvm-svn: 37931
2007-07-06 01:00:49 +00:00
eaa82198c4
Add OptionalDefOperand to stand for optionally defined result.
...
llvm-svn: 37930
2007-07-06 01:00:16 +00:00
9546a5c7de
Initial ARM JIT support by Raul Fernandes Herbster.
...
llvm-svn: 37926
2007-07-05 21:15:40 +00:00
de9c825859
Proper flag __alloca call
...
llvm-svn: 37923
2007-07-05 20:36:08 +00:00
cee44d3d1d
Doh
...
llvm-svn: 37917
2007-07-05 17:21:33 +00:00
a6246f4346
Unbreak the build.
...
llvm-svn: 37915
2007-07-05 17:13:56 +00:00
085314b455
Unbreak the build.
...
llvm-svn: 37914
2007-07-05 17:13:19 +00:00
e16561cd5d
Here is the bulk of the sanitizing.
...
Almost all occurrences of "bytecode" in the sources have been eliminated.
llvm-svn: 37913
2007-07-05 17:07:56 +00:00
6d1cf76c97
the arm backend is not building, temporarily disable it.
...
llvm-svn: 37911
2007-07-05 16:11:52 +00:00
94f04c6fc9
Reflects the chanegs made to PredicateOperand.
...
llvm-svn: 37898
2007-07-05 07:18:20 +00:00
a7f77599a4
Added ARM::CPSR to represent ARM CPSR status register.
...
llvm-svn: 37897
2007-07-05 07:17:13 +00:00
7e90b11550
Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.
...
llvm-svn: 37896
2007-07-05 07:15:27 +00:00
aa3b8014bd
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
...
llvm-svn: 37895
2007-07-05 07:13:32 +00:00
49ffa1e488
Added ARM::CPSR to represent ARM CPSR status register.
...
llvm-svn: 37894
2007-07-05 07:11:03 +00:00
ea4a82bcfb
PPC conditional branch predicate does not change after isel.
...
llvm-svn: 37893
2007-07-05 07:09:50 +00:00
756d15ac6f
- Added zero_reg def to stand for register 0.
...
- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.
llvm-svn: 37892
2007-07-05 07:09:09 +00:00
0721084327
Do not check isPredicated() on non-predicable instructions.
...
llvm-svn: 37891
2007-07-05 07:06:46 +00:00
3d7008cd49
Refactor X87 instructions. As a side effect, all
...
their names are changed.
llvm-svn: 37876
2007-07-04 21:07:47 +00:00
8590f920c7
Support generation of GR64 to MMX code in the JIT.
...
llvm-svn: 37866
2007-07-04 01:29:22 +00:00
3053244b27
Allow a GR64 to be moved into an MMX register via the "movd" instruction.
...
Still need to have JIT generate this code.
llvm-svn: 37863
2007-07-04 00:19:54 +00:00
c2a6089b8b
Some spacing fixes. Cosmetic.
...
llvm-svn: 37853
2007-07-03 17:07:33 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
f9ae1c6001
Vector results may be returned in XMM0 and XMM1, not just XMM0. With
...
the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.
llvm-svn: 37844
2007-07-02 16:21:53 +00:00
2660cef6d7
Convert .cvsignore files
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llvm-svn: 37801
2007-06-29 16:35:07 +00:00
58d1eacd80
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
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llvm-svn: 37790
2007-06-29 01:25:06 +00:00
444d3ca53d
No vector fneg.
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llvm-svn: 37786
2007-06-29 00:18:15 +00:00
3bd318e298
Type of vector extract / insert index operand should be iPTR.
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llvm-svn: 37784
2007-06-29 00:01:20 +00:00
f413419a72
Set implied features based upon the CPU's feature list.
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llvm-svn: 37768
2007-06-27 23:34:06 +00:00
1cbdcac409
Remove a redundant newline in the asm output for ELF .rodata sections.
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llvm-svn: 37756
2007-06-27 15:09:47 +00:00
335c65e9a4
Silence a warning.
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llvm-svn: 37737
2007-06-26 18:31:22 +00:00
e8c1e428f2
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
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extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
2e84e3f7b7
Make minor adjustments to whitespace and comments to reduce differences
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between SSE1 instructions and their respective SSE2 analogues.
llvm-svn: 37718
2007-06-25 15:44:19 +00:00
33209bd6b8
Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet.
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llvm-svn: 37717
2007-06-25 15:19:03 +00:00
e33c4b739b
Say AT&T instead of Intel in the comments for AT&T support.
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llvm-svn: 37716
2007-06-25 15:11:25 +00:00
0c550df9d2
Fix the build.
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llvm-svn: 37705
2007-06-22 16:59:54 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
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TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
485531ea9b
Quote complex names for Darwin X86 and ARM.
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llvm-svn: 37700
2007-06-22 00:54:56 +00:00
77d61e6f6d
Be more conservative of duplicating blocks.
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llvm-svn: 37669
2007-06-19 23:55:02 +00:00
c3c949b473
Allow predicated immediate ARM to ARM calls.
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llvm-svn: 37659
2007-06-19 21:05:09 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
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for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
7936d91f70
describe an argument, hide it.
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llvm-svn: 37650
2007-06-19 05:46:06 +00:00
Dale Johannesen