3e18e504ae
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
...
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
86e0119822
Fold the adjust_trampoline intrinsic into
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init_trampoline. There is now only one
trampoline intrinsic.
llvm-svn: 41841
2007-09-11 14:10:23 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
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Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
9a25d98c86
Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.
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llvm-svn: 41597
2007-08-30 05:52:20 +00:00
43318839c9
Added method to get Mips register numbers
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Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack.
Stack offset calculation bug fixed!
llvm-svn: 41529
2007-08-28 05:13:42 +00:00
14033fb5cb
Changed stack allocation On LowerFORMAL_ARGUMENTS.
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Added comments about new stack allocation.
Expand SelectCC for i32 results
llvm-svn: 41527
2007-08-28 05:08:16 +00:00
cfd1638e2d
Mask directive completed with CalleeSave info
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Comments for Mips directives added.
llvm-svn: 41526
2007-08-28 05:06:17 +00:00
f55a785e56
Added methods to record SPOffsets from LowerFORMAL_ARGUMENTS
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llvm-svn: 41525
2007-08-28 05:04:41 +00:00
b10580ac1e
InlineAsm asm support for integer registers added
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llvm-svn: 41225
2007-08-21 16:09:25 +00:00
d4b9945a21
Instruction Itinerary attribution fixed
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llvm-svn: 41224
2007-08-21 16:06:45 +00:00
9fbef51078
MipsHi now has ouput flag
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MipsAdd SDNode created to add support to an Add opcode which supports input flag
Added an instruction itinerary to all instruction classes
Added branches with zero cond codes
Now call clobbers all non-callee saved registers
Call w/ register support added
Added DelaySlot to branch and load instructions
Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions
llvm-svn: 41161
2007-08-18 02:37:46 +00:00
eabe61b080
Fixed stack frame addressing bug
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llvm-svn: 41160
2007-08-18 02:19:09 +00:00
f3c55807f2
support for Schedule included on Mips.td
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llvm-svn: 41159
2007-08-18 02:18:07 +00:00
4bd7f4db9f
Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress
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fixed to generate instructions (add, lui) glued!
llvm-svn: 41158
2007-08-18 02:16:30 +00:00
833a1f9b55
Couple of small changes. Delay Slot handle header declared.
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Newline added after macros at function init on generated asm!
llvm-svn: 41157
2007-08-18 02:05:24 +00:00
5792189590
Added InstrItinClass support for instruction formats
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llvm-svn: 41156
2007-08-18 02:01:28 +00:00
0c530638c7
Branch Analysis and InsertNoop inserted into header files
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llvm-svn: 41155
2007-08-18 01:59:45 +00:00
a746512fc5
createMipsDelaySlotFillerPass added to mips codegen runtime
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llvm-svn: 41154
2007-08-18 01:58:15 +00:00
7b616f5742
Added Branch Analysis support
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Added InsertNoop support
llvm-svn: 41153
2007-08-18 01:56:48 +00:00
e8d1c52cd4
LowerRETURNADDR removed since it was wrong and does not have utility yet!
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MipsAdd opcode added
llvm-svn: 41152
2007-08-18 01:54:09 +00:00
87beec9afb
InstrItineraryData support on added.
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Added Mips3 ISA feature (needed when supporting R4000 machines)
llvm-svn: 41151
2007-08-18 01:52:27 +00:00
0b97ce752c
A Pass to insert Nops on intructions with DelaySlot
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llvm-svn: 41150
2007-08-18 01:50:47 +00:00
415ded5d5a
Mips generic fallback instruction schedule support!
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llvm-svn: 41149
2007-08-18 01:46:44 +00:00
5f6a9da530
More explicit keywords.
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llvm-svn: 40757
2007-08-02 21:21:54 +00:00
644f917358
Support for trampolines, except for X86 codegen which is
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still under discussion.
llvm-svn: 40549
2007-07-27 12:58:54 +00:00
cf0a5349de
Don't ignore the return value of AsmPrinter::doInitialization and
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AsmPrinter::doFinalization.
llvm-svn: 40487
2007-07-25 19:33:14 +00:00
ac1591be42
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
bcda5e20c9
Added support for Mips specific GAS directives
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Fixed print immediate
Fixed Identation on MipsISelDAGToDAG.cpp
llvm-svn: 39764
2007-07-11 23:24:41 +00:00
6c8c748e4d
Added support for framepointer
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Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!
llvm-svn: 39763
2007-07-11 23:21:31 +00:00
77dbdcabf2
Now that stack is represented the right way, LOA starts at 0
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llvm-svn: 39761
2007-07-11 23:17:41 +00:00
4449e5dd7f
Fixed AddLiveOut issues
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FI's created the write way to represent Mips stack
llvm-svn: 39760
2007-07-11 23:16:16 +00:00
c5affeccbd
Removed unused immediate PatLeaf, fixed lui instruction
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llvm-svn: 39759
2007-07-11 22:47:02 +00:00
753e37027f
Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog
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llvm-svn: 39758
2007-07-11 22:44:21 +00:00
09d73c0305
Assert when TLS is not implemented.
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llvm-svn: 39737
2007-07-11 17:19:51 +00:00
517290ae52
The various "getModuleMatchQuality" implementations should return
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zero if they see a target triple they don't understand.
llvm-svn: 38463
2007-07-09 17:25:29 +00:00
35e43c49b0
Initial Mips support, here we go! =)
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- Modifications from the last patch included
(issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.
llvm-svn: 37461
2007-06-06 07:42:06 +00:00
Evan Cheng