Commit Graph

312478 Commits

Author SHA1 Message Date
Aaron Puchert dc087de14c Minor renaming as suggested in review [NFC]
See D59455.

llvm-svn: 356430
2019-03-19 00:14:46 +00:00
Eric Fiselier 0f8041b6e2 Remove unused try catch blocks from old debug tests
llvm-svn: 356429
2019-03-19 00:00:30 +00:00
Fangrui Song 1092fc9057 [ELF] Allow sh_entsize to be unrelated to sh_addralign and not a power of 2
Summary:
This implements Rui Ueyama's idea in PR39044.
I've checked that ld.bfd and gold do not have the power-of-2 requirement
and do not require sh_entsize to be a multiple of sh_align.

Now on the updated test merge-entsize.s, all the 3 linkers happily
create .rodata that is not 3-byte aligned.

This has a use case in Linux arch/x86/crypto/sha512-avx2-asm.S
It uses sh_entsize of 640, which is not a power of 2.
See https://github.com/ClangBuiltLinux/linux/issues/417

Reviewers: ruiu, espindola

Reviewed By: ruiu

Subscribers: nickdesaulniers, E5ten, emaste, arichardson, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59478

llvm-svn: 356428
2019-03-18 23:49:18 +00:00
Aaron Puchert ad4d52a501 Thread safety analysis: Add note for unlock kind mismatch
Summary:
Similar to D56967, we add the existing diag::note_locked_here to tell
the user where we saw the locking that isn't matched correctly.

Reviewers: aaron.ballman, delesley

Reviewed By: aaron.ballman

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D59455

llvm-svn: 356427
2019-03-18 23:26:54 +00:00
Reid Kleckner ed350f73c1 [asan] Disable -Wfortify-source in intentional OOB tests
Needed after r356397

llvm-svn: 356426
2019-03-18 23:03:46 +00:00
Reid Kleckner 61c9b7cb9f [MS] Skip vbase construction in abstract class ctors
As background, when constructing a complete object, virtual bases are
constructed first. If an exception is thrown later in the ctor, those
virtual bases are destroyed, so sema marks the relevant constructors and
destructors of virtual bases as referenced. If necessary, they are
emitted.

However, an abstract class can never be used to construct a complete
object. In the Itanium C++ ABI, this works out nicely, because we never
end up emitting the "complete" constructor variant, only the "base"
constructor variant, which can be called by constructors of derived
classes. Clang's Sema::MarkBaseAndMemberDestructorsReferenced is aware
of this optimization, and it does not mark ctors and dtors of virtual
bases referenced when the constructor of an abstract class is emitted.

In the Microsoft ABI, there are no complete/base variants, so before
this change, the constructor of an abstract class could reference ctors
and dtors of a virtual base without marking them referenced. This could
lead to unresolved symbol errors at link time, as reported in PR41065.

The fix is to implement the same optimization as Sema: If the class is
abstract, don't bother initializing its virtual bases. The "is this
class the most derived class" check in the constructor will never pass,
and the virtual base constructor calls are always dead. Skip them.

I think Richard noticed this missed optimization back in 2016 when he
was implementing inheriting constructors. I wasn't able to find any bugs
or email about it, though.

Fixes PR41065

llvm-svn: 356425
2019-03-18 22:41:50 +00:00
Nikita Popov 3e9770d2dc Revert "[ValueTracking][InstSimplify] Support min/max selects in computeConstantRange()"
This reverts commit 106f0cdefb.

This change impacts the AMDGPU smed3.ll and umed3.ll codegen tests.

llvm-svn: 356424
2019-03-18 22:26:27 +00:00
Craig Topper 8b653d0308 [X86] Add gcc rotate intrinsics to ia32intrin.h
This is another attempt at what Erich Keane tried to do in r355322.

This adds rolb, rolw, rold, rolq and their ror equivalent as always_inline wrappers around __builtin_rotate* which will lower to funnel shift intrinsics in IR.

Additionally, when _MSC_VER is not defined we will define _rotl, _lrotl, _rotr, _lrotr as macros to one of the always_inline intrinsics mentioned above. Making sure that _lrotl/_lrotr use either 32 or 64 bit based on the size of long. These need to be macros because we have builtins with the same name for MS compatibility, but _MSC_VER isn't always defined when those builtins are enabled.

We also define _rotwl and _rotwr as macros aliasing to rolw/rorw just like gcc to complete the set. These don't need to be gated with _MSC_VER because these aren't MS builtins.

I've added tests both for non-MS and -ms-extensions with and without _MSC_VER being defined.

Differential Revision: https://reviews.llvm.org/D59346

llvm-svn: 356423
2019-03-18 22:25:57 +00:00
Kostya Serebryany 9aac4c1be3 [libFuzzer] document -len_control
llvm-svn: 356422
2019-03-18 22:20:47 +00:00
Eric Fiselier cc703de62f Fix test failures after debug mode changes
llvm-svn: 356421
2019-03-18 22:12:09 +00:00
Craig Topper 1dd518da7d [X86] Add coverage for 16-bit and 64-bit versions of bsf/bsr/bt/btc/btr/bts in the assembly tests that are supposed to provide full coverage. Add coverage for cwtl/cltq/cwtd/cqto as well.
llvm-svn: 356420
2019-03-18 22:06:19 +00:00
Craig Topper b24bdf626a [X86] Disable CQTO and CLTQ instructions in the assembly parser outside 64-bit mode.
llvm-svn: 356419
2019-03-18 22:06:14 +00:00
Julian Lettner 1814355655 [NFC][TSan][libdispatch] Fix test for dispatch_apply[_f]
* Array index out of bounds: 100 iterations, but size of array is 2.
* Unmatched barrier_init (2) with barrier_wait (200)
* Number of iterations must be smaller than the available parallelism
  for the queue, otherwise we deadlock (since every barrier_wait call
  blocks the thread).

Scary: All of this worked reliably in gcd-apply.mm (for Darwin)

Rievewed By: kubamracek

Differential Revision: https://reviews.llvm.org/D59510

llvm-svn: 356418
2019-03-18 21:55:41 +00:00
Eric Fiselier 61b302f94f Remove exception throwing debug mode handler support.
Summary:
The reason libc++ implemented a throwing debug mode handler was for ease of testing. Specifically,
I thought that if a debug violation aborted, we could only test one violation per file. This made
it impossible to test debug mode. Which throwing behavior we could test more!

However, the throwing approach didn't work either, since there are debug violations underneath noexcept
functions. This lead to the introduction of `_NOEXCEPT_DEBUG`, which was only noexcept when debug
mode was off.

Having thought more and having grown wiser, `_NOEXCEPT_DEBUG` was a horrible decision. It was
viral, it didn't cover all the cases it needed to, and it was observable to the user -- at worst
changing the behavior of their program.

  This patch removes the throwing debug handler, and rewrites the debug tests using 'fork-ing' style
  death tests.

Reviewers: mclow.lists, ldionne, thomasanderson

Reviewed By: ldionne

Subscribers: christof, arphaman, libcxx-commits, #libc

Differential Revision: https://reviews.llvm.org/D59166

llvm-svn: 356417
2019-03-18 21:50:12 +00:00
Jason Molenda 2d5e7adf26 A target definition file that may work for
Aarch32 Cortex-M target processor debugging.

<rdar://problem/48448564> 

llvm-svn: 356416
2019-03-18 21:39:54 +00:00
Nikita Popov 106f0cdefb [ValueTracking][InstSimplify] Support min/max selects in computeConstantRange()
Add support for min/max flavor selects in computeConstantRange(),
which allows us to fold comparisons of a min/max against a constant
in InstSimplify. This was suggested by spatel as an alternative
approach to D59378. I've also added the infinite looping test from
that revision here.

Differential Revision: https://reviews.llvm.org/D59506

llvm-svn: 356415
2019-03-18 21:35:19 +00:00
Nikita Popov 930341ba30 [InstCombine] Add tests for add nuw + uaddo; NFC
Baseline tests for D59471 (InstCombine of `add nuw` and `uaddo` with
constants).

Patch by Dan Robertson.

Differential Revision: https://reviews.llvm.org/D59472

llvm-svn: 356414
2019-03-18 21:35:09 +00:00
Craig Topper e732bc6bea [X86] Allow any 8-bit immediate to be used with BT/BTC/BTR/BTS not just sign extended 8-bit immediates.
We need to allow [128,255] in addition to [-128, 127] to match gas.

llvm-svn: 356413
2019-03-18 21:33:59 +00:00
Alex Langford b4a3b29d16 [CMake] Set LLVM_DEFAULT_EXTERNAL_LIT in standalone build correctly on windows
LLVM installed llvm-lit with a .py suffix on windows. Let's match that
behavior here.

llvm-svn: 356412
2019-03-18 21:32:31 +00:00
Amara Emerson a140276a1e [GlobalISel] Include missing change from r356396
Forgot to add a change to relax some asserts in r356396.

llvm-svn: 356411
2019-03-18 21:29:21 +00:00
Sam Clegg b7708ec87f [WebAssembly] Don't override default implementation of isOffsetFoldingLegal. NFC.
The default implementation does we want and is going to more compatible
with dynamic linking (-fPIC) support that is planned.

This is NFC because currently we only build wasm with
`-relocation-model=static` which in turn means that the default
`isOffsetFoldingLegal` always returns true today.

Differential Revision: https://reviews.llvm.org/D54661

llvm-svn: 356410
2019-03-18 21:21:12 +00:00
Nikita Popov f89343bc47 [ValueTracking][InstSimplify] Move abs handling into computeConstantRange(); NFC
This is preparation for D59506. The InstructionSimplify abs handling
is moved into computeConstantRange(), which is the general place for
such calculations. This is NFC and doesn't affect the existing tests
in test/Transforms/InstSimplify/icmp-abs-nabs.ll.

Differential Revision: https://reviews.llvm.org/D59511

llvm-svn: 356409
2019-03-18 21:20:03 +00:00
Nikita Popov 05baa9ee1a [InstSimplify] Add additional icmp of min/max tests; NFC
These are baseline tests for D59506.

llvm-svn: 356408
2019-03-18 21:19:56 +00:00
Craig Topper f086e562f9 [X86] Use relocImm in the ROL8ri/ROL16ri/ROL32ri/ROL64ri patterns to be consistent with the ROR patterns.
llvm-svn: 356407
2019-03-18 20:43:15 +00:00
Craig Topper 0b9c640fe0 [X86] Replace uses of i64immSExt32_su with i64relocImmSExt32_su.
For the i8, i16, and i32 instructions we were using a relocImm. Presumably we should for i64 as well.

llvm-svn: 356406
2019-03-18 20:43:09 +00:00
Michael Liao efb4f9e568 [AMDGPU] Enable code selection using `s_mul_hi_u32`/`s_mul_hi_i32`.
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59501

llvm-svn: 356405
2019-03-18 20:40:09 +00:00
Jake Ehrlich 5049c3422d [llvm-objcopy] Make .build-id linking atomic
This change makes linking into .build-id atomic and safe to use.
Some users under particular workflows are reporting that this races
more than half the time under particular conditions.

llvm-svn: 356404
2019-03-18 20:35:18 +00:00
Nikita Popov c1d4fc8a62 [InstCombine] Improve with.overflow intrinsic tests; NFC
- Do not use unnamed values in saddo tests
- Add tests for canonicalization of a constant arg0

Patch by Dan Robertson.

Differential Revision: https://reviews.llvm.org/D59476

llvm-svn: 356403
2019-03-18 20:08:35 +00:00
Sam Clegg 1d716acf76 Restore comment regarding why Reloc::PIC_ can't be PIC
The original change back in rL29307 explained this but it was
lost somewhere along the way.

Differential Revision: https://reviews.llvm.org/D59445

llvm-svn: 356402
2019-03-18 20:04:34 +00:00
Davide Italiano 65dc65216e [API] Remove unneded LLDB_DISABLE_PYTHON markers.
llvm-svn: 356401
2019-03-18 20:02:27 +00:00
Alexandre Ganea 9af9f500d1 Fix flat-error-unsupported-gpu-hsa test
Differential Revision: https://reviews.llvm.org/D59505

llvm-svn: 356400
2019-03-18 19:38:04 +00:00
Tim Renouf cfdfba996b [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic
Allow the clamp modifier on vop3 int arithmetic instructions in assembly
and disassembly.

This involved adding a clamp operand to the affected instructions in MIR
and MC, and thus having to fix up several places in codegen and MIR
tests.

Differential Revision: https://reviews.llvm.org/D59267

Change-Id: Ic7775105f02a985b668fa658a0cd7837846a534e
llvm-svn: 356399
2019-03-18 19:35:44 +00:00
Tim Renouf 2e94f6e584 [AMDGPU] Asm/disasm v_cndmask_b32_e64 with abs/neg source modifiers
This commit allows v_cndmask_b32_e64 with abs, neg source
modifiers on src0, src1 to be assembled and disassembled.

This does appear to be allowed, even though they are floating point
modifiers and the operand type is b32.

To do this, I added src0_modifiers and src1_modifiers to the
MachineInstr, which involved fixing up several places in codegen and mir
tests.

Differential Revision: https://reviews.llvm.org/D59191

Change-Id: I69bf4a8c73ebc65744f6110bb8fc4e937d79fbea
llvm-svn: 356398
2019-03-18 19:25:39 +00:00
Erik Pilkington b6e16ea006 [Sema] Add some compile time _FORTIFY_SOURCE diagnostics
These diagnose overflowing calls to subset of fortifiable functions. Some
functions, like sprintf or strcpy aren't supported right not, but we should
probably support these in the future. We previously supported this kind of
functionality with -Wbuiltin-memcpy-chk-size, but that diagnostic doesn't work
with _FORTIFY implementations that use wrapper functions. Also unlike that
diagnostic, we emit these warnings regardless of whether _FORTIFY_SOURCE is
actually enabled, which is nice for programs that don't enable the runtime
checks.

Why not just use diagnose_if, like Bionic does? We can get better diagnostics in
the compiler (i.e. mention the sizes), and we have the potential to diagnose
sprintf and strcpy which is impossible with diagnose_if (at least, in languages
that don't support C++14 constexpr). This approach also saves standard libraries
from having to add diagnose_if.

rdar://48006655

Differential revision: https://reviews.llvm.org/D58797

llvm-svn: 356397
2019-03-18 19:23:45 +00:00
Amara Emerson 8627178d46 Revert r356304: remove subreg parameter from MachineIRBuilder::buildCopy()
After review comments, it was preferred to not teach MachineIRBuilder about
non-generic instructions beyond using buildInstr().

For AArch64 I've changed the buildCopy() calls to buildInstr() + a
separate addReg() call.

This also relaxes the MachineIRBuilder's COPY checking more because it may
not always have a SrcOp given to it.

llvm-svn: 356396
2019-03-18 19:20:10 +00:00
Alexandre Ganea 4aeea4cc42 [DebugInfo][PDB] Don't write empty debug streams
Before, empty debug streams were written as 8 bytes (4 bytes signature + 4 bytes for the GlobalRefs count).

With this patch, unused empty streams aren't emitted anymore. Modules now encode 65535 as an 'unused stream' value, by convention.
Also fix the * Linker * contrib section which wasn't correctly emitted previously.

Differential Revision: https://reviews.llvm.org/D59502

llvm-svn: 356395
2019-03-18 19:13:23 +00:00
Tim Renouf 8723a56551 [MsgPack][AMDGPU] Fix unflushed raw_string_ostream bugs on windows expensive checks bot
This fixes a couple of unflushed raw_string_ostream bugs in recent
commits that only show up on a bot building on windows with expensive
checks.

Differential Revision: https://reviews.llvm.org/D59396

Change-Id: I9c6208325503b3ee0786b4b688e13fc24a15babf
llvm-svn: 356394
2019-03-18 19:00:46 +00:00
Craig Topper f07062a798 [X86] Rename imm8_su/imm16_su/imm32_su to relocImm8_su/relocImm16_su/relocImm32_su/ to accurately reflect what they are.
llvm-svn: 356393
2019-03-18 18:54:06 +00:00
Warren Ristow ad7d0ded2e [SCEV] Guard movement of insertion point for loop-invariants
This reinstates r347934, along with a tweak to address a problem with
PHI node ordering that that commit created (or exposed). (That commit
was reverted at r348426, due to the PHI node issue.)

Original commit message:

r320789 suppressed moving the insertion point of SCEV expressions with
dev/rem operations to the loop header in non-loop-invariant situations.
This, and similar, hoisting is also unsafe in the loop-invariant case,
since there may be a guard against a zero denominator. This is an
adjustment to the fix of r320789 to suppress the movement even in the
loop-invariant case.

This fixes PR30806.

Differential Revision: https://reviews.llvm.org/D57428

llvm-svn: 356392
2019-03-18 18:52:35 +00:00
Adhemerval Zanella 270249de2b [AArch64] Small fix for getIntImmCost
It uses the generic AArch64_IMM::expandMOVImm to get the correct
number of instruction used in immediate materialization.

Reviewers: efriedma

Differential Revision: https://reviews.llvm.org/D58461

llvm-svn: 356391
2019-03-18 18:50:58 +00:00
Adhemerval Zanella a3cefa5d64 [AArch64] Optimize floating point materialization
This patch follows some ideas from r352866 to optimize the floating
point materialization even further. It changes isFPImmLegal to
considere up to 2 mov instruction or up to 5 in case subtarget has
fused literals.

The rationale is the cost is the same for mov+fmov vs. adrp+ldr; but
the mov+fmov sequence is always better because of the reduced d-cache
pressure. The timings are still the same if you consider movw+movk+fmov
vs. adrp+ldr will be fused (although one instruction longer).

Reviewers: efriedma

Differential Revision: https://reviews.llvm.org/D58460

llvm-svn: 356390
2019-03-18 18:45:57 +00:00
Adhemerval Zanella 664c1ef528 [TargetLowering] Add code size information on isFPImmLegal. NFC
This allows better code size for aarch64 floating point materialization
in a future patch.

Reviewers: evandro

Differential Revision: https://reviews.llvm.org/D58690

llvm-svn: 356389
2019-03-18 18:40:07 +00:00
Alexey Bataev f6a53d63a1 [OPENMP] Set scheduling for doacross loops as schedule, 1.
The default scheduling for doacross loops is changed from static to
static, 1.

llvm-svn: 356388
2019-03-18 18:40:00 +00:00
Adhemerval Zanella 8a595b1d2e [AArch64] Refactor floating point materialization. NFC
It splits the login of actual instruction emission away from the logic
that figures out the appropriate sequence on AArch64ExpandPseudo::expandMOVImm.
The new function AArch64_IMM::expandMOVImm, which return the list of the 
instructions to materialize the immediate constant, is implemented on a 
separated unit because it will be used in a subsequent patch to optimize
floating point materialization.

Reviewers: efriedma

Differential Revision: https://reviews.llvm.org/D58915

llvm-svn: 356387
2019-03-18 18:23:23 +00:00
Louis Dionne 0c962cb5c8 [libc++][NFC] Promote CMake comment to an actual option description
llvm-svn: 356386
2019-03-18 18:18:01 +00:00
Michael Liao 3c2aadbe67 [AMDGPU] Add the missing clang change of the experimental buffer fat pointer
llvm-svn: 356385
2019-03-18 18:11:37 +00:00
Craig Topper c2b35ebc1d [X86] Remove the _alt forms of (V)CMP instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Similar to previous change done for VPCOM and VPCMP

Differential Revision: https://reviews.llvm.org/D59468

llvm-svn: 356384
2019-03-18 17:59:59 +00:00
Sanjay Patel 08b5e68ef6 [InstCombine] add/adjust test for NaN checks; NFC
llvm-svn: 356383
2019-03-18 17:37:05 +00:00
Nirav Dave 55c921f4bf [DAG] Cleanup unused node in SimplifySelectCC.
Delete temporarily constructed node uses for analysis after it's use,
holding onto original input nodes. Ideally this would be rewritten
without making nodes, but this appears relatively complex.

Reviewers: spatel, RKSimon, craig.topper

Subscribers: jdoerfert, hiraditya, deadalnix, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57921

llvm-svn: 356382
2019-03-18 17:02:38 +00:00
Michael Liao c131e0e2ae [MVT] Fix typos in comment. NFC.
llvm-svn: 356381
2019-03-18 16:57:40 +00:00