ea447da8a8
Add definitions for TEST instructions
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llvm-svn: 6498
2003-06-01 01:56:39 +00:00
70f158330c
Add new cmovne32 instruction
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llvm-svn: 6496
2003-06-01 00:05:15 +00:00
9ed31bc497
Fix bug: CBackend/2003-05-31-MissingStructName.ll
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llvm-svn: 6495
2003-05-31 23:30:52 +00:00
3b7974d40c
New testcase
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llvm-svn: 6494
2003-05-31 23:27:10 +00:00
2b1329611b
Fix bug: FunctionResolve/2003-05-31-AllInternalDecls.ll
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llvm-svn: 6486
2003-05-31 21:57:06 +00:00
306f8b4934
Add support for: -o -
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llvm-svn: 6485
2003-05-31 21:47:16 +00:00
a71b979201
New testcase
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llvm-svn: 6484
2003-05-31 21:33:08 +00:00
bb25391608
New testcase for behavior we depend on.
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llvm-svn: 6483
2003-05-31 21:14:45 +00:00
080436820e
Fix bug: FuncResolve/2003-05-31-InternalDecl.ll
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Count resolutions correctly.
llvm-svn: 6482
2003-05-31 21:08:45 +00:00
2111527574
New testcase
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llvm-svn: 6481
2003-05-31 21:04:39 +00:00
709c1d469b
Simplify funcresolve a bit more
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llvm-svn: 6480
2003-05-31 20:44:46 +00:00
5ef98de61c
Fix bug: FunctionResolve/2003-05-31-FuncPointerResolve.ll
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llvm-svn: 6479
2003-05-31 20:33:31 +00:00
9c6e99cae6
Add another testcase
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llvm-svn: 6478
2003-05-31 20:33:09 +00:00
1fcfd4eb61
New testcase
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llvm-svn: 6477
2003-05-31 20:21:13 +00:00
e2d74c1c81
Fixed comment width, changed arg to be const, fixed indentation, removed unnecessary includes.
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llvm-svn: 6476
2003-05-31 20:01:37 +00:00
d9460e12f5
* Correct title
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* Give credit to John for making the page
llvm-svn: 6475
2003-05-31 19:55:19 +00:00
384f6ba403
*** empty log message ***
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llvm-svn: 6474
2003-05-31 16:46:21 +00:00
ef56a0fb6a
Made a single common InvalidRegNum = -1.
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llvm-svn: 6473
2003-05-31 07:44:07 +00:00
12067b6598
Renamed a variable.
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llvm-svn: 6472
2003-05-31 07:43:41 +00:00
1a06ec6655
Support for annul/pred and other future flags on op codes.
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Support for recording the physical register for implcit references.
llvm-svn: 6471
2003-05-31 07:43:01 +00:00
24ce4d8eb8
Minor changes.
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llvm-svn: 6470
2003-05-31 07:41:54 +00:00
ad83684c77
Added MachineCodeForInstruction object as an argument to
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TmpInstruction constructors because every TmpInstruction object has
to be registered with a MachineCodeForInstruction to prevent leaks.
This simplifies the user's code.
llvm-svn: 6469
2003-05-31 07:41:24 +00:00
c468882155
Allow explicit physical registers for implicit operands.
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llvm-svn: 6468
2003-05-31 07:39:06 +00:00
465f9b6738
Changes to allow explicit physical register arguments that have been
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preallocated. While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.
llvm-svn: 6467
2003-05-31 07:37:05 +00:00
ba6f8e274a
Several bug fixes: globals in call operands were not being pulled out;
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globals in some other places may not have been pulled out either;
globals in phi operands were being put just before the phi instead of
in the predecessor basic blocks.
llvm-svn: 6466
2003-05-31 07:34:57 +00:00
a83804a29a
Extensive changes to the way code generation occurs for function
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call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
llvm-svn: 6465
2003-05-31 07:32:01 +00:00
96b801ab56
Reverting previous beautification changes.
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llvm-svn: 6464
2003-05-31 07:27:17 +00:00
d2b29c8a9e
Fixed rewriting of branches -- they now work forward and backward.
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llvm-svn: 6463
2003-05-31 06:26:48 +00:00
bf69b7fe69
Removed useless code -- the byte order of output code is correct as is.
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llvm-svn: 6462
2003-05-31 06:26:06 +00:00
23937091f0
The 'rd' register is consistently mentioned last in instruction definitions.
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Created new classes from which instructions inherit their ordering of fields.
llvm-svn: 6461
2003-05-31 06:25:19 +00:00
c4f029f8ba
* Put back into action SLL/SRL/SRA{r,i}6 instructions
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* Fixed page numbers referring to the Sparc manual
llvm-svn: 6460
2003-05-31 06:24:29 +00:00
8d5316769f
Code beautification, no functional changes.
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llvm-svn: 6459
2003-05-31 06:22:37 +00:00
a48e258ab6
3 more bugs from the SPEC codes and from richards_benchmark.c
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llvm-svn: 6458
2003-05-31 04:45:56 +00:00
0b3a70c25b
Enabling some of these passes causes lli to break
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llvm-svn: 6457
2003-05-31 04:23:04 +00:00
87cbd97710
The actual order of parameters in a 2-reg-immediate assembly instructions is
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"rs1, imm, rd": most importantly, rd goes last.
llvm-svn: 6456
2003-05-31 04:22:26 +00:00
1656f61b93
New testcase
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llvm-svn: 6454
2003-05-30 21:03:00 +00:00
d137d6ba65
Since malloc is no longer used, no need to free() memory.
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Fixed BasicBlock patching by supplying correct type for the displacement.
llvm-svn: 6453
2003-05-30 20:39:37 +00:00
736e6172dc
When converting virtual registers to immediate constants, change the opcode.
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llvm-svn: 6452
2003-05-30 20:36:27 +00:00
94908b010e
Added saveBBreferences() for BasicBlock resolution.
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llvm-svn: 6451
2003-05-30 20:32:45 +00:00
027b3d899f
getValueOp() now takes a MachineInstr as well as a MachineOperand.
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llvm-svn: 6450
2003-05-30 20:32:01 +00:00
5bf351c880
Added:
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* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers
llvm-svn: 6449
2003-05-30 20:17:33 +00:00
0757de607a
Fixed the namespace to match SparcInternals.h; added notes on some missing
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sections of instructions.
llvm-svn: 6448
2003-05-30 20:15:59 +00:00
8747377292
The register types need to be visible outside of the class to be useful.
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For one, converting register numbers based on class in the code emitter.
llvm-svn: 6447
2003-05-30 20:12:42 +00:00
a853af587a
Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.
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Code beautification for the rest of the code: changed layout to match the rest
of the code base.
llvm-svn: 6446
2003-05-30 20:11:56 +00:00
c1830a472a
Make LLI behave just like LLC with regard to the compile passes it uses.
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llvm-svn: 6444
2003-05-30 20:00:13 +00:00
fdb2f4b7cd
Add SRoA pass to gccas
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llvm-svn: 6442
2003-05-30 19:24:06 +00:00
49fac80010
Move indvars pass after mem2reg pass where it is more likely to be useful
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llvm-svn: 6441
2003-05-30 19:23:10 +00:00
0078d9c5bb
Okay totally give up on trying to optimize aggregates that cannot be completely
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broken up into their elements. Too many programs break because of this.
llvm-svn: 6440
2003-05-30 19:22:14 +00:00
39dfa6a920
Made the register and immediate versions of instructions consecutive.
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llvm-svn: 6439
2003-05-30 19:14:01 +00:00
d847be0539
add a check that allows the SRoA pass to avoid breaking programs, even if their
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behavior is technically undefined
llvm-svn: 6438
2003-05-30 18:09:57 +00:00
Chris Lattner