1b420ac4c8
Make machine verifier check the first instruction of the last bundle instead of
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the last instruction of a basic block.
llvm-svn: 158468
2012-06-14 20:51:13 +00:00
a33db65bd9
Make comment slightly more helpful.
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llvm-svn: 158467
2012-06-14 20:37:15 +00:00
5d19452f3f
Revert r158454: Allow SROA to look at a vector type... Its breaking the vectorise buildbot
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This reverts commit 12c1f86ffa731e2952c80d2cc577000c96b8962c.
llvm-svn: 158462
2012-06-14 18:32:52 +00:00
45877fa011
misched: disable SSA check pending PR13112.
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llvm-svn: 158461
2012-06-14 17:48:49 +00:00
a7e6d58a87
Recommit r158407: Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access. Now with additional fix and test for indexing into a vector inside a struct
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llvm-svn: 158454
2012-06-14 16:38:13 +00:00
27bdc671ed
MipsLongBranch.cpp: Tweak llvm::next() to appease msvc.
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llvm-svn: 158446
2012-06-14 12:29:48 +00:00
b0ec375b96
Replace assertion failure for badly formatted CPS instrution with error message.
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llvm-svn: 158445
2012-06-14 10:48:04 +00:00
ac96b764ea
Cleanup whitespace.
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llvm-svn: 158443
2012-06-14 06:08:19 +00:00
c2bc2d106b
InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).
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uno && ueq was converted to ueq, it should be converted to uno.
llvm-svn: 158441
2012-06-14 05:57:42 +00:00
d74b1c1a48
Fix Mips/CMakeLists.txt.
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llvm-svn: 158437
2012-06-14 01:23:55 +00:00
a215929d5f
Add file MipsLongBranch.cpp.
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llvm-svn: 158436
2012-06-14 01:22:24 +00:00
a1b142f97c
Remove code in MipsAsmPrinter and MipsMCInstLower.
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llvm-svn: 158434
2012-06-14 01:20:12 +00:00
eb36522a4d
Add long branch expansion pass for MIPS.
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llvm-svn: 158433
2012-06-14 01:19:35 +00:00
64f8df28ed
Add AT to the list of registers clobbered by branches so that it is available
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as a scratch register when they are expanded to long branches.
llvm-svn: 158432
2012-06-14 01:17:59 +00:00
194a8773ea
In MipsRegisterInfo::eliminateFrameIndex, call Mips::loadImmediate
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to load an immediate that does not fit into 16-bit.
llvm-svn: 158431
2012-06-14 01:17:36 +00:00
2372c8bb5f
In MipsFrameLowering::emitPrologue and emitEpilogue, call Mips::loadImmediate
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to load an immediate that does not fit into 16-bit. Also, take into
consideration the global base register slot on the stack when computing the
stack size.
llvm-svn: 158430
2012-06-14 01:17:13 +00:00
acd1a7dc68
Define function MipsInstrInfo::GetInstSizeInBytes, which will be called to
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compute the size of basic blocks in a function. Also, define a function which
emits a series of instructions to load an immediate.
llvm-svn: 158429
2012-06-14 01:16:45 +00:00
0c76448471
In MipsISelDAGToDAG.cpp, store the global base register to a stack frame object.
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Long-branches need access to the global base register to get the destination
address.
llvm-svn: 158428
2012-06-14 01:16:15 +00:00
51c70c62cf
Add methods to MipsFunctionInfo for initializing and accessing the stack frame
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object for the global base register.
This is the first of a series of patches which implements long branch expansion
for MIPS.
llvm-svn: 158427
2012-06-14 01:15:36 +00:00
5ac78681c1
Bundle jump/branch instructions with the instructions in the delay slot in
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delay slot filler pass of MIPS, per suggestion of Jakob Stoklund Olesen.
This change, along with the fix in r158154, enables machine verification
to be run after delay slot filling.
llvm-svn: 158426
2012-06-13 23:25:52 +00:00
df5205ef3d
Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
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pattern:
(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
"tjt" is a TargetJumpTable node.
llvm-svn: 158419
2012-06-13 20:33:18 +00:00
1daf8c2a16
Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
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llvm-svn: 158414
2012-06-13 19:33:32 +00:00
9586618c58
Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
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llvm-svn: 158413
2012-06-13 19:06:08 +00:00
f0273603f5
Implement fastcc calling convention for MIPS.
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llvm-svn: 158410
2012-06-13 18:06:00 +00:00
ab7d788eb5
Fix pattern for MKMSK instruction.
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llvm-svn: 158409
2012-06-13 17:59:12 +00:00
e2fe809772
Revert "Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access"
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This reverts commit 51786e0aaec76b973205066bd44f7f427b21969f.
llvm-svn: 158408
2012-06-13 17:55:22 +00:00
e1d4e8b563
Allow SROA to look at a vector type and see if the offset is out of range to be replaced with a scalar access
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llvm-svn: 158407
2012-06-13 17:30:34 +00:00
444fd42634
Fix building ThreadLocal.cpp with --disable-threads.
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llvm-svn: 158405
2012-06-13 16:30:06 +00:00
f294921e24
*typo: Cyles changed to Cycles
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llvm-svn: 158404
2012-06-13 15:53:04 +00:00
409d8ae165
It is possible for several constants which aren't individually absorbing to
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combine to the absorbing element. Thanks to nbjoerg on IRC for pointing this
out.
llvm-svn: 158399
2012-06-13 12:15:56 +00:00
318a89ddac
When linearizing a multiplication, return at once if we see a factor of zero,
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since then the entire expression must equal zero (similarly for other operations
with an absorbing element). With this in place a bunch of reassociate code for
handling constants is dead since it is all taken care of when linearizing. No
intended functionality change.
llvm-svn: 158398
2012-06-13 09:42:13 +00:00
71dc02d659
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them.
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llvm-svn: 158396
2012-06-13 07:18:53 +00:00
9898614854
Add another missing 64-bit itinerary definition for the PPC A2 core.
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llvm-svn: 158393
2012-06-13 05:55:09 +00:00
d33f4efbfd
SimplifyCFG: fold unconditional branch to its predecessor if profitable.
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This patch extends FoldBranchToCommonDest to fold unconditional branches.
For unconditional branches, we fold them if it is easy to update the phi nodes
in the common successors.
rdar://10554090
llvm-svn: 158392
2012-06-13 05:43:29 +00:00
1c66b87f7d
Eliminate struct TableGenBackend.
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TableGen backends are simply written as functions now.
Patch by Sean Silva!
llvm-svn: 158389
2012-06-13 05:15:49 +00:00
21371766d1
Clean up trailing blanks in Mips16InstrFormats.td
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Patch by Reed Kotler.
llvm-svn: 158382
2012-06-13 02:42:47 +00:00
5fa541231b
disable use of directive .set nomicromips
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until this directive is pushed in gas to open source fsf
Patch by Reed Kotler.
llvm-svn: 158381
2012-06-13 02:41:14 +00:00
344fb64fa3
sched: fix latency of memory dependence chain edges for consistency.
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For store->load dependencies that may alias, we should always use
TrueMemOrderLatency, which may eventually become a subtarget hook. In
effect, we should guarantee at least TrueMemOrderLatency on at least
one DAG path from a store to a may-alias load.
This should fix the standard mode as well as -enable-aa-sched-mi".
llvm-svn: 158380
2012-06-13 02:39:03 +00:00
5b90645abb
sched: Avoid trivially redundant DAG edges. Take the one with higher latency.
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llvm-svn: 158379
2012-06-13 02:39:00 +00:00
3fe00f29ad
1. fix places where immed is used in place of imm to be consistent with
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non mips16
2. fix some comments to change OPcode->EXTEND for extended instructions
Patch by Reed Kotler.
llvm-svn: 158378
2012-06-13 02:37:54 +00:00
79c39da135
Add some missing 64-bit itinerary definitions for the PPC A2 core.
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llvm-svn: 158373
2012-06-12 20:32:29 +00:00
72aea01b6e
Use DenseMap as SmallMap workaround rather than std::map, at Chandler's request.
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llvm-svn: 158371
2012-06-12 20:26:43 +00:00
67cd591989
Use std::map rather than SmallMap because SmallMap assumes that the value has
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POD type, causing memory corruption when mapping to APInts with bitwidth > 64.
Merge another crash testcase into crash.ll while there.
llvm-svn: 158369
2012-06-12 20:16:51 +00:00
c6916f88a8
[arm-fast-isel] Add support for -arm-long-calls.
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Patch by Jush Lu <jush.msn@gmail.com>.
llvm-svn: 158368
2012-06-12 19:25:13 +00:00
8c33dde666
Split out the PPC instruction class IntSimple from IntGeneral.
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On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
llvm-svn: 158366
2012-06-12 19:01:24 +00:00
f1cc96ab50
Fixes for PPC host detection and features.
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POWER4 is a 64-bit CPU (better matched to the 970).
The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750).
Patch by Andreas Tobler.
llvm-svn: 158363
2012-06-12 16:39:23 +00:00
d7aeefebd6
Now that Reassociate's LinearizeExprTree can look through arbitrary expression
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topologies, it is quite possible for a leaf node to have huge multiplicity, for
example: x0 = x*x, x1 = x0*x0, x2 = x1*x1, ... rapidly gives a value which is x
raised to a vast power (the multiplicity, or weight, of x). This patch fixes
the computation of weights by correctly computing them no matter how big they
are, rather than just overflowing and getting a wrong value. It turns out that
the weight for a value never needs more bits to represent than the value itself,
so it is enough to represent weights as APInts of the same bitwidth and do the
right overflow-avoiding dance steps when computing weights. As a side-effect it
reduces the number of multiplies needed in some cases of large powers. While
there, in view of external uses (eg by the vectorizer) I made LinearizeExprTree
static, pushing the rank computation out into users. This is progress towards
fixing PR13021.
llvm-svn: 158358
2012-06-12 14:33:56 +00:00
59b0ee8a56
Reapply r158337, this time properly protect Darwin/PPC host CPU use with __ppc__.
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Original commit message:
Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().
Both the new Linux functionality and the old Darwin functions have been moved.
This change also allows this information to be queried directly by clang and
other frontends (clang, for example, will now have real -mcpu=native support).
llvm-svn: 158349
2012-06-12 03:03:13 +00:00
c6dc4d75fd
Satisfy C++ aliasing rules, per suggestion by Chandler.
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llvm-svn: 158346
2012-06-12 01:06:16 +00:00
f8f128606c
Revert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName()."
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This commit broke most of the PowerPC unit tests when running on
Intel/Apple.
llvm-svn: 158345
2012-06-12 00:58:40 +00:00
Akira Hatanaka