replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
100,766 Commits 2 Branches 0 Tags 1.8 GiB
Commit Graph

65 Commits

Author SHA1 Message Date
Jim Grosbach fb116aed60 Add source Record* reference to PatternToMatch. Allows better diagnostics. 
llvm-svn: 121196
 2010-12-07 23:05:49 +00:00
Jim Grosbach 8656d82b5b Trailing whitespace. 
llvm-svn: 121167
 2010-12-07 19:36:07 +00:00
Jim Grosbach e99956eb3e Change assert to diagnostic. Message still needs work, but it's better than 
an assert, at least.

llvm-svn: 121166
 2010-12-07 19:35:36 +00:00
Chris Lattner d8adec70f3 factor the operand list (and related fields/operations) out of 
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
 2010-11-01 04:03:32 +00:00
Eric Christopher 6490bf6072 Allow strict subclasses of register classes, this way we can handle 
ARM instructions with:

foo GPR, rGPR

which happens a lot.

llvm-svn: 112025
 2010-08-25 04:58:56 +00:00
Eric Christopher 98f0ea6ade Fix comment. 
llvm-svn: 111996
 2010-08-24 23:21:59 +00:00
Eric Christopher d84dbb5caf Remove predicate workaround, we're going to require that predicate 
and optional def operands are handled in the backend support.

llvm-svn: 111220
 2010-08-17 01:18:37 +00:00
Eric Christopher e1270c64e3 Filter out patterns that have PredicateOperands. 
llvm-svn: 109572
 2010-07-28 01:52:23 +00:00
Eric Christopher 62ac5ca22d 80-col. 
llvm-svn: 109407
 2010-07-26 17:53:07 +00:00
Eric Christopher bebb8c5f86 Hack around extracts that aren't easy to process. 
llvm-svn: 109043
 2010-07-21 22:07:19 +00:00
Jakob Stoklund Olesen 4a52e2f6a7 Replace copyRegToReg with COPY in FastISelEmitter. 
llvm-svn: 108071
 2010-07-11 03:53:50 +00:00
Dan Gohman d7b5ce3312 Reapply bottom-up fast-isel, with several fixes for x86-32: 
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039
 2010-07-10 09:00:22 +00:00
Bob Wilson 6586e9b203 --- Reverse-merging r107947 into '.': 
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987
 2010-07-09 16:37:18 +00:00
Dan Gohman cc40c76382 These changes should have accompanied r107943. 
llvm-svn: 107947
 2010-07-09 00:59:16 +00:00
Dan Gohman e75704369d Revert 107840 107839 107813 107804 107800 107797 107791. 
Debug info intrinsics win for now.

llvm-svn: 107850
 2010-07-08 01:00:56 +00:00
Dan Gohman ffe64b1ee5 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it 
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791
 2010-07-07 16:47:08 +00:00
Dan Gohman 388fa73f03 Minor code simplification. 
llvm-svn: 104845
 2010-05-27 16:25:05 +00:00
Jakob Stoklund Olesen 1c69646e99 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
 2010-05-24 14:48:12 +00:00
Dan Gohman 1a1b51ff59 Add initial kill flag support to FastISel. 
llvm-svn: 103529
 2010-05-11 23:54:07 +00:00
Dan Gohman 779c69bbc5 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Chris Lattner 6c2d178957 add plumbing for handling multiple result nodes 
in some more places.

llvm-svn: 99366
 2010-03-24 00:41:19 +00:00
Chris Lattner f144725ebc major surgery on tblgen: generalize TreePatternNode 
to maintain a list of types (one for each result of
the node) instead of a single type.  There are liberal
hacks added to emulate the old behavior in various
situations, but they can start disolving now.

llvm-svn: 98999
 2010-03-19 21:37:09 +00:00
Chris Lattner 9aec14b560 look up instructions by record, not by name. 
llvm-svn: 98904
 2010-03-19 00:07:20 +00:00
Chris Lattner cabe037b2d Completely rewrite tblgen's type inference mechanism, 
changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!

llvm-svn: 98534
 2010-03-15 06:00:16 +00:00
Dan Gohman 404a984780 Don't use the ISD::NodeType enum for SDNode opcodes, as CodeGen 
uses several kinds of opcode values which are not declared within
that enum. This fixes PR5946.

llvm-svn: 92794
 2010-01-05 22:26:32 +00:00
Duncan Sands 2fbeaf084f Remove some unused variables and methods warned about by 
icc (#177, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81106
 2009-09-06 08:33:48 +00:00
Owen Anderson 9f94459d24 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Daniel Dunbar 38a22bffdc Replace std::iostreams with raw_ostream in TableGen. 
- Sorry, I can't help myself.

 - No intended functionality change.

llvm-svn: 74742
 2009-07-03 00:10:29 +00:00
Dale Johannesen 4ff70e389e TableGen for fast isel seems to assume an 'imm' 
operand is the last in a pattern.  There is no
reason this should be true (although apparently
it always is right now).

llvm-svn: 72232
 2009-05-21 22:25:49 +00:00
Evan Cheng 4a0bf66eb8 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
llvm-svn: 62762
 2009-01-22 09:10:11 +00:00
Dan Gohman 6e979020cd Add support for having multiple predicates on a TreePatternNode. 
This will allow predicates to be composed, which will allow the
predicate definitions to become less redundant, and eventually
will allow DAGISelEmitter.cpp to emit less redundant code.

llvm-svn: 57562
 2008-10-15 06:17:21 +00:00
Dan Gohman b486350b15 Move the primary fast-isel top-level comments to FastISel.cpp, where 
they'll be a little more visible. Also, update and reword them a bit.

llvm-svn: 56877
 2008-09-30 20:48:29 +00:00
Evan Cheng ca14c07175 Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs. 
llvm-svn: 55893
 2008-09-08 08:39:33 +00:00
Evan Cheng 09638d34a5 Fix indentation of generated code. 
llvm-svn: 55876
 2008-09-07 08:23:06 +00:00
Evan Cheng 7cab17af29 Ignore multi-instruction patterns. e.g. 
def : Pat<(i8 (trunc GR32:$src)),
          (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))>

llvm-svn: 55875
 2008-09-07 08:19:51 +00:00
Evan Cheng 24422d4928 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. 
llvm-svn: 55679
 2008-09-03 00:03:49 +00:00
Owen Anderson 0673a8af14 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
llvm-svn: 55545
 2008-08-29 17:45:56 +00:00
Dan Gohman d58f3e36d0 Add a target callback for FastISel. 
llvm-svn: 55512
 2008-08-28 23:21:34 +00:00
Owen Anderson 787f100462 Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling. 
llvm-svn: 55480
 2008-08-28 18:06:12 +00:00
Dan Gohman 6d153b02c9 Update a comment to reflect recent changes. 
llvm-svn: 55418
 2008-08-27 16:18:22 +00:00
Dan Gohman 5ca269e684 Basic FastISel support for floating-point constants. 
llvm-svn: 55401
 2008-08-27 01:09:54 +00:00
Dan Gohman 44003cc354 Refactor a bunch of FastISelEmitter code into a helper class, and 
put each major step in a separate function. This makes the high
level sequence of events easier to follow.

llvm-svn: 55385
 2008-08-26 21:21:20 +00:00
Owen Anderson 3ea3efec44 We need to check that the return type is correct, even in cases where we don't 
have a return type that differs from the operand types.

llvm-svn: 55376
 2008-08-26 18:50:00 +00:00
Owen Anderson 6f2db7238b Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes. 
llvm-svn: 55349
 2008-08-26 01:22:59 +00:00
Owen Anderson 5f334d8215 Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic. No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch. 
llvm-svn: 55347
 2008-08-26 00:42:26 +00:00
Owen Anderson 8dd01ccdd8 Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return 
type down.  This is not currently used.

llvm-svn: 55345
 2008-08-25 23:58:18 +00:00
Owen Anderson 5952cca7d1 Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns 
with return types that differ from their input types.  This is not yet used.

llvm-svn: 55344
 2008-08-25 23:43:09 +00:00
Owen Anderson 32635dbfb2 Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.

llvm-svn: 55325
 2008-08-25 20:20:32 +00:00
Dan Gohman 9b29ec7ba9 Add a few comments. 
llvm-svn: 55157
 2008-08-22 00:28:15 +00:00