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30937 Commits

Author SHA1 Message Date
Lauro Ramos Venancio 25d4052af6 Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Evan Cheng c5bc763f50 Turn on GEP index sinking by default. 
llvm-svn: 35127
 2007-03-16 18:32:30 +00:00
Evan Cheng 0a9d0cabaf Stupid bug. 
llvm-svn: 35126
 2007-03-16 17:50:20 +00:00
Bill Wendling 144b8bbf17 And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Evan Cheng 009ea54262 Sink a binary expression into its use blocks if it is a loop invariant 
computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123
 2007-03-16 08:46:27 +00:00
Evan Cheng 0e34d6af6b Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Evan Cheng a2a2fd1e55 Added isLegalAddressExpression hook to test if the given expression can be 
folded into target addressing mode for the given type.

llvm-svn: 35121
 2007-03-16 08:42:32 +00:00
Evan Cheng 2ae53613ca These forward declarations are not needed. 
llvm-svn: 35120
 2007-03-16 08:41:06 +00:00
Nick Lewycky 4f73de2b4e Add more comments and update to new asm syntax. 
Add new micro-optimizations.

Add icmp predicate snuggling. Given %x ULT 4, "icmp ugt %x, 2" becomes
"icmp eq %x, 3". This doesn't apply in any non-trivial cases yet due to missing
support for NE values in ValueRanges.

llvm-svn: 35119
 2007-03-16 02:37:39 +00:00
Bill Wendling e31034125c Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00
Evan Cheng 88de94a4fb Debugging output stuff. 
llvm-svn: 35117
 2007-03-15 21:19:28 +00:00
Reid Spencer 17e9e8b9af Regenerate. 
llvm-svn: 35116
 2007-03-15 03:26:42 +00:00
Reid Spencer 74d4d172bd Revert last changes as they introduced other problems. 
llvm-svn: 35115
 2007-03-15 03:25:34 +00:00
Evan Cheng 70e16d5e17 ARM isel should match ldr x +/- x * (2^n) to ldr [x, +/- x, lsl #log2(n)]. 
llvm-svn: 35114
 2007-03-14 23:26:40 +00:00
Reid Spencer 2ece31b4ce Regenerate. 
llvm-svn: 35113
 2007-03-14 23:13:06 +00:00
Reid Spencer c2dd8280e2 The sign information was not propagating into the rename map so only the 
last entry stored in the map could be retrieved for a given integer type.
Propagating the sign information required an invasive change to ensure that
all ValueRef (ValID) instances get the right sign information as well. Also,
put in some assertions to ensure the RenameMap always gives us out the type
that is expected.

This fixes PR1256 and
test/Assembler/2007-03-14-UgpradeLocalSignless.ll

llvm-svn: 35112
 2007-03-14 23:11:45 +00:00
Reid Spencer 4040130a86 For PR1256: 
Carry sign with ValID and make TypeInfo sortable (useful in a map).

llvm-svn: 35111
 2007-03-14 23:08:04 +00:00
Reid Spencer dca9687de6 Test case for PR1256. 
llvm-svn: 35110
 2007-03-14 23:07:24 +00:00
Evan Cheng b9e3db67fb Estimate a cost using the possible number of scratch registers required and use 
it as a late BURR scheduling tie-breaker.
Intuitively, it's good to push down instructions whose results are liveout so
their long live ranges won't conflict with other values which are needed inside
the BB. Further prioritize liveout instructions by the number of operands which
are calculated within the BB.

llvm-svn: 35109
 2007-03-14 22:43:40 +00:00
Evan Cheng a1779b9739 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
llvm-svn: 35108
 2007-03-14 22:11:11 +00:00
Evan Cheng 71face25ef Notes about codegen issues. 
llvm-svn: 35107
 2007-03-14 21:03:53 +00:00
Duncan Sands a413e0825f Test that the size of a view converted object is determined by the target 
type, not the source type.

llvm-svn: 35106
 2007-03-14 20:24:53 +00:00
Evan Cheng e278f30a52 Clean up. 
llvm-svn: 35105
 2007-03-14 20:20:19 +00:00
Evan Cheng eb76f7c6fd Oops. 
llvm-svn: 35104
 2007-03-14 19:44:58 +00:00
Jim Laskey 6e8a2f4738 Change e-mail address. 
llvm-svn: 35103
 2007-03-14 19:32:21 +00:00
Jim Laskey 2211f496ff Add link to exception handling. 
llvm-svn: 35102
 2007-03-14 19:31:19 +00:00
Jim Laskey 7248e711bd Adding credit for PPC changes. 
llvm-svn: 35101
 2007-03-14 19:30:33 +00:00
Jim Laskey 6956773583 First draft of exception handling doc. 
llvm-svn: 35100
 2007-03-14 19:29:42 +00:00
Jeff Cohen eb9dccf63d Make older versions of bison happy. 
llvm-svn: 35099
 2007-03-14 15:27:17 +00:00
Jeff Cohen 137a16ea95 Fix for VS 2005 problem supplied by Morten Ofstad. 
llvm-svn: 35098
 2007-03-14 15:25:21 +00:00
Evan Cheng dda4c32db3 X86-64 JIT is in large code model. Need stubs for direct calls. 
llvm-svn: 35097
 2007-03-14 10:51:55 +00:00
Evan Cheng 386dfc9251 x86-64 JIT stub codegen. 
llvm-svn: 35096
 2007-03-14 10:48:08 +00:00
Evan Cheng e1a95206e3 Preliminary support for X86-64 JIT stub codegen. 
llvm-svn: 35095
 2007-03-14 10:44:30 +00:00
Zhou Sheng d8c645b0ba ShiftAmt might equal to zero. Handle this situation. 
llvm-svn: 35094
 2007-03-14 09:07:33 +00:00
Zhou Sheng b912844554 Enable KnownZero/One.clear(). 
llvm-svn: 35093
 2007-03-14 03:21:24 +00:00
Evan Cheng b59d60da40 New test. 
llvm-svn: 35091
 2007-03-13 23:31:47 +00:00
Evan Cheng ca6fab953f This got better. 
llvm-svn: 35090
 2007-03-13 23:26:41 +00:00
Evan Cheng 2874855302 Try schedule def + use closer whne Sethi-Ullman numbers are the same. 
e.g.
t1 = op t2, c1
t3 = op t4, c2
and the following instructions are both ready.
t2 = op c3
t4 = op c4

Then schedule t2 = op first.
i.e.
t4 = op c4
t2 = op c3
t1 = op t2, c1
t3 = op t4, c2

This creates more short live intervals which work better with the register
allocator.

llvm-svn: 35089
 2007-03-13 23:25:11 +00:00
Evan Cheng 72a8bcf238 AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] 
llvm-svn: 35088
 2007-03-13 21:05:54 +00:00
Evan Cheng 507eefa757 Zero is always a legal AM immediate. 
llvm-svn: 35087
 2007-03-13 20:37:59 +00:00
Evan Cheng b5eb932c93 Correct type info for isLegalAddressImmediate() check. 
llvm-svn: 35086
 2007-03-13 20:34:37 +00:00
Duncan Sands 3240cdb339 Test support for arrays with non-zero first index. 
llvm-svn: 35084
 2007-03-13 15:12:35 +00:00
Nicolas Geoffray 7aad92868c Stack and register alignment of call arguments in the ELF ABI 
llvm-svn: 35083
 2007-03-13 15:02:46 +00:00
Chris Lattner d1bce956b4 ifdef out some dead code. 
Fix PR1244 and Transforms/InstCombine/2007-03-13-CompareMerge.ll

llvm-svn: 35082
 2007-03-13 14:27:42 +00:00
Chris Lattner 091e75bbde testcase for PR1244 
llvm-svn: 35081
 2007-03-13 14:25:35 +00:00
Zhou Sheng ebe634e662 For expression like 
"APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth)",
to handle ShiftAmt == BitWidth situation, use zextOrCopy() instead of
zext().

llvm-svn: 35080
 2007-03-13 06:40:59 +00:00
Zhou Sheng b9c3707e97 Add zextOrCopy() into APInt for convenience. 
llvm-svn: 35079
 2007-03-13 06:16:26 +00:00
Zhou Sheng af4341d441 In APInt version ComputeMaskedBits(): 
1. Ensure VTy, KnownOne and KnownZero have same bitwidth.
  2. Make code more efficient.

llvm-svn: 35078
 2007-03-13 02:23:10 +00:00
Evan Cheng 818242bbaf Implement getTargetLowering() or else LSR won't be using ARM specific hooks. 
llvm-svn: 35077
 2007-03-13 01:20:42 +00:00
Evan Cheng b7004fd889 More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale. 
llvm-svn: 35076
 2007-03-12 23:37:10 +00:00