Commit Graph

30 Commits

Author SHA1 Message Date
Brian Gaeke 7efd5fcb3a Mark the instructions that have delay slots with the hasDelaySlot flag.
Add some comments.

llvm-svn: 16611
2004-09-30 04:04:48 +00:00
Brian Gaeke ede068a8d3 Tell the target description that calls clobber registers O0...O5.
llvm-svn: 16594
2004-09-29 20:45:05 +00:00
Brian Gaeke 3a340dd7cd FITOD is spelled "fitod", not "fitos". Ouch.
llvm-svn: 16591
2004-09-29 19:59:07 +00:00
Brian Gaeke da371d9cf3 Add new FpMOVD pseudo-instruction, used to move doubles around.
llvm-svn: 16574
2004-09-29 03:27:29 +00:00
Misha Brukman 3c08658d56 Combine the F2 and F3 instruction classes into one file for simplicity
llvm-svn: 16484
2004-09-22 21:38:42 +00:00
Misha Brukman 8f951e579b Remove ClassPrefix variable as it's no longer used.
llvm-svn: 15586
2004-08-09 19:13:29 +00:00
Misha Brukman 0eb9cee698 The (future) SparcV8 JIT would do well to have a class prefix.
llvm-svn: 15583
2004-08-09 18:13:09 +00:00
Chris Lattner 4504b95801 I'm pretty sure that ba is branch always, which is a barrier. Brg should
check this :)

llvm-svn: 15357
2004-07-31 02:24:37 +00:00
Brian Gaeke 135b870f72 Add a class for pseudo-instructions. Use it.
Add IMPLICIT_USE and IMPLICIT_DEF, a la X86.

llvm-svn: 14884
2004-07-16 10:32:10 +00:00
Brian Gaeke 7b4722e62c Add floating-point branches and compares. Compares don't complete
until the next cycle, and there's no interlock, so they effectively
have a delay slot.

llvm-svn: 14686
2004-07-08 09:08:22 +00:00
Brian Gaeke b3d33c7994 Add FITOS, FITOD, and F{ADD,SUB,MUL,DIV}{S,D}.
llvm-svn: 14444
2004-06-27 22:53:56 +00:00
Brian Gaeke 27966ba77b Add FSTOD and FDTOS conversion instructions.
llvm-svn: 14372
2004-06-24 21:22:09 +00:00
Brian Gaeke c8e1b5abe8 Rename the load and store opcodes. The non-fp ones only have one
variant worth worrying about; the fp ones have two.
Add fp stores.

llvm-svn: 14361
2004-06-24 07:36:59 +00:00
Brian Gaeke 75f3738969 Fix jmpl.
Add some FP moves.

llvm-svn: 14225
2004-06-18 06:28:10 +00:00
Brian Gaeke 51d3c7b05b Add load instructions for floating-point registers.
llvm-svn: 14217
2004-06-18 05:19:27 +00:00
Brian Gaeke eca9546dc3 Set the isBranch and isTerminator flags on branch instructions correctly.
Add a FIXME about the (currently unused) JMPL instructions.

llvm-svn: 14210
2004-06-17 22:34:29 +00:00
Brian Gaeke 91bf7cb79b Add a bunch more branches
llvm-svn: 13422
2004-05-08 06:08:29 +00:00
Brian Gaeke d18b330605 Add ADD with immediate
llvm-svn: 13420
2004-05-08 05:26:55 +00:00
Brian Gaeke b56f1c9c10 Add forms of CMP, SUBCC, and a few branches, and some comments.
llvm-svn: 13419
2004-05-08 04:21:32 +00:00
Chris Lattner bb22d5a564 andd subcc instructions which is used to create the 'cmp' pseudo instruction
llvm-svn: 12744
2004-04-07 05:04:01 +00:00
Chris Lattner 8406cf3046 Fix encoding of existing shift instructions, add rr shifts
llvm-svn: 12739
2004-04-07 04:26:57 +00:00
Chris Lattner fcdf82a19f Add a bunch more instructions
llvm-svn: 12737
2004-04-07 04:06:46 +00:00
Brian Gaeke 5524d54c02 Add UDIV, SDIV, and a few variants of WR.
llvm-svn: 12733
2004-04-07 04:01:00 +00:00
Brian Gaeke d4869e4107 Add load, store, and NOP instructions.
Fix up comments.

llvm-svn: 12631
2004-04-02 20:53:37 +00:00
Brian Gaeke ae22ce5370 Add UMULrr and SMULrr instructions.
llvm-svn: 12452
2004-03-16 22:37:13 +00:00
Brian Gaeke c65b97d4f6 Sort stanzas into Sparc V8 book page number order.
Add RET, RETL.  Rename SAVE, RESTORE & JMPL for consistency.

llvm-svn: 12185
2004-03-06 05:32:13 +00:00
Brian Gaeke 92c95f812d Subtract instructions; minor cleanups
llvm-svn: 12111
2004-03-04 04:37:45 +00:00
Brian Gaeke 956fb06a4a Simple copyConstantToReg support, SETHIi and ORri
llvm-svn: 12107
2004-03-04 00:56:25 +00:00
Brian Gaeke 165ff998e0 Support add - note, still missing important copyConstantToRegister stuff
llvm-svn: 12106
2004-03-03 23:03:14 +00:00
Chris Lattner e40fd90b0b Tab completion is our friend.
llvm-svn: 11957
2004-02-28 19:45:39 +00:00