c16f77fb27
Recommit 116986 with capitalization typo fixed.
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llvm-svn: 116993
2010-10-21 03:57:26 +00:00
f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
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llvm-svn: 116992
2010-10-21 03:40:16 +00:00
078db00f1d
Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it
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compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.
llvm-svn: 116991
2010-10-21 03:34:22 +00:00
9e00f27e14
Revert r116983, which is breaking all the buildbots.
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llvm-svn: 116987
2010-10-21 03:11:16 +00:00
f608ac4db9
Major update of the MicroBlaze backend. The new features are:
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1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
llvm-svn: 116986
2010-10-21 03:09:55 +00:00
15c2ac90ec
Add missing scheduling itineraries for transfers between core registers and VFP registers.
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llvm-svn: 116983
2010-10-21 01:12:00 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
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llvm-svn: 116981
2010-10-21 00:48:00 +00:00
a65f914bb0
Add encoding for moving a value between two ARM core registers and a doublework
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extension register.
llvm-svn: 116970
2010-10-20 23:37:40 +00:00
058190507b
Add encodings for movement between ARM core registers and single-precision
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registers.
llvm-svn: 116961
2010-10-20 22:44:54 +00:00
55a028680c
Add some comments.
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llvm-svn: 116957
2010-10-20 22:04:02 +00:00
87066f0677
More accurate estimate / tracking of register pressure.
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- Initial register pressure in the loop should be all the live defs into the
loop. Not just those from loop preheader which is often empty.
- When an instruction is hoisted, update register pressure from loop preheader
to the original BB.
- Treat only use of a virtual register as kill since the code is still SSA.
llvm-svn: 116956
2010-10-20 22:03:58 +00:00
ff37675c72
Fix crash introduced in 116852. 8573915.
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llvm-svn: 116955
2010-10-20 22:03:37 +00:00
ef3ba55e52
Cut unneeded global variable.
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llvm-svn: 116953
2010-10-20 22:01:39 +00:00
89f6613e76
Handle _GLOBAL_OFFSET_TABLE_ correctly.
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llvm-svn: 116932
2010-10-20 16:46:08 +00:00
710a2d9d46
Enable using vdup for vector constants which are splat of
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integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's. 8003375.
llvm-svn: 116852
2010-10-19 20:00:17 +00:00
63c7608c34
Re-enable register pressure aware machine licm with fixes. Hoist() may have
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erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
llvm-svn: 116845
2010-10-19 18:58:51 +00:00
e8b3711ae9
Fixing r116753 r116756 r116777
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The failures in r116753 r116756 were caused by a python issue -
Python likes to append 'L' suffix to stringified numbers if the number
is larger than a machine int. Unfortunately, this causes a divergence of
behavior between 32 and 64 bit python versions.
I re-crafted elf-dump/common_dump to take care of these issues by:
1. always printing 0x (makes for easy sed/regex)
2. always print fixed length (exactly 2 + numBits/4 digits long)
by mod ((2^numBits) - 1)
3. left-padded with '0'
There is a residual common routine that is also used by
macho-dump (dataToHex) , so I left the 'section_data' test values alone.
llvm-svn: 116823
2010-10-19 17:39:10 +00:00
418204e523
Revert r116781 "- Add a hook for target to determine whether an instruction def
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is", which breaks some nightly tests.
llvm-svn: 116816
2010-10-19 17:14:24 +00:00
2072db24ed
GlobalOpt: EvaluateFunction() must not evaluate stores to weak_odr globals.
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Fixes PR8389.
llvm-svn: 116812
2010-10-19 16:47:23 +00:00
18d3e435cb
Add test case mov.ll for PTX device function
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llvm-svn: 116806
2010-10-19 13:21:51 +00:00
e73bc89093
Fix PR8300 by remembering to keep the bitcast in all cases.
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llvm-svn: 116788
2010-10-19 02:02:57 +00:00
8249dfe6ce
- Add a hook for target to determine whether an instruction def is
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"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
llvm-svn: 116781
2010-10-19 00:55:07 +00:00
eac5e381cc
Speculatively revert 116753 and 116756 to attempt to fix the bots.
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llvm-svn: 116777
2010-10-19 00:19:49 +00:00
b6d61dc291
Support alignment for NEON vld-lane and vst-lane instructions.
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llvm-svn: 116776
2010-10-19 00:16:32 +00:00
49843c0162
Added a few tweaks to the Intel Descriptor-table support instructions to allow
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word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
llvm-svn: 116773
2010-10-19 00:01:44 +00:00
7b92c2a9a0
Revert r116220 - thus turning arm fast isel back on by default.
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llvm-svn: 116762
2010-10-18 22:53:53 +00:00
d4cc3d420a
Get rid of unneeded FormatOutput global variable
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llvm-svn: 116756
2010-10-18 21:59:38 +00:00
eae048885d
Changed elf-dump to output hex format by default.
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Also updated tests.
llvm-svn: 116753
2010-10-18 21:32:41 +00:00
408beac597
Don't pass the raw invalid pointer used to represent conflicting
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TBAA information to AliasAnalysis.
llvm-svn: 116751
2010-10-18 21:28:00 +00:00
fe8abf88a0
Add a basic testcase for TBAA-aware LICM.
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llvm-svn: 116745
2010-10-18 21:00:09 +00:00
fba9f74932
Implement R_386_GOT32.
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llvm-svn: 116744
2010-10-18 20:47:21 +00:00
0a5314fdb3
Relocate with .bss instead of using the symbol. Matches gas behavior.
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llvm-svn: 116741
2010-10-18 20:25:33 +00:00
f7a5e20372
Run tbaa before basicaa, since that's how it's expected to be used.
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llvm-svn: 116731
2010-10-18 18:45:59 +00:00
e3dc9e2ea1
Produce ELF::R_386_GOTPC relocations.
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llvm-svn: 116728
2010-10-18 18:36:12 +00:00
33fcde9b9c
Make TypeBasedAliasAnalysis default to doing nothing, with a command-line
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option to enable it.
llvm-svn: 116722
2010-10-18 18:17:47 +00:00
02538ac4d3
Make BasicAliasAnalysis a normal AliasAnalysis implementation which
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does normal initialization and normal chaining. Change the default
AliasAnalysis implementation to NoAlias.
Update StandardCompileOpts.h and friends to explicitly request
BasicAliasAnalysis.
Update tests to explicitly request -basicaa.
llvm-svn: 116720
2010-10-18 18:04:47 +00:00
b9783dd9bc
Added a handful of x86-32 instructions that were missing so that llvm-mc would
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be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
llvm-svn: 116716
2010-10-18 17:04:36 +00:00
3521f8467d
Produce a R_386_PLT32 when needed. Moved the default cases of switches to the
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start for consistency.
llvm-svn: 116715
2010-10-18 16:58:03 +00:00
4464e0858f
Handle GOTOFF correctly on i386.
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llvm-svn: 116711
2010-10-18 16:38:04 +00:00
5f2034c455
Improve lowering of sext to i128 on SPU.
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The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.
llvm-svn: 116701
2010-10-18 09:34:19 +00:00
4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
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single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
0d14b5b0fa
Unbreak test on non-COFF targets.
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llvm-svn: 116669
2010-10-16 11:27:13 +00:00
17990d5690
MC-COFF: Add support for default-null weak externals.
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llvm-svn: 116666
2010-10-16 08:25:57 +00:00
5e683250ee
X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
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if any floating point arguments are passed to an external function.
llvm-svn: 116665
2010-10-16 08:25:41 +00:00
18e4fed3fa
Generalize MemCpyOpt's handling of call slot forwarding to function properly when the call slot
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forwarding is implemented with a load/store pair rather than a memcpy.
llvm-svn: 116637
2010-10-15 22:52:12 +00:00
3ba051a4f6
llvmc: Add a test for the -c flag.
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llvm-svn: 116611
2010-10-15 19:30:49 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
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llvm-svn: 116588
2010-10-15 17:15:16 +00:00
f28cc03802
FileCheckize
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llvm-svn: 116581
2010-10-15 16:06:42 +00:00
fbcf0db7ee
Refactor code a bit and avoid creating unnecessary entries in the string
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map.
llvm-svn: 116579
2010-10-15 15:39:06 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
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have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
0b5c743811
Simplify test file a bit.
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llvm-svn: 116540
2010-10-14 23:32:44 +00:00
89efff3763
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
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are just forms of that instruction).
llvm-svn: 116538
2010-10-14 23:29:18 +00:00
8b6a9c1574
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
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and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
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pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
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llvm-svn: 116498
2010-10-14 18:54:27 +00:00
bee6e9f8e0
Remove some code duplication.
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llvm-svn: 116484
2010-10-14 16:34:44 +00:00
793d141b7d
Comments.
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llvm-svn: 116476
2010-10-14 13:43:20 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
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here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
0441c6cba0
Add encoding for 'fmstat'.
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llvm-svn: 116466
2010-10-14 01:19:34 +00:00
0825f3e441
- Add encodings for multiply add/subtract instructions in all their glory.
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- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
b9681ad442
fix a bug I introduced, no idea how this didn't repro right.
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llvm-svn: 116462
2010-10-14 00:30:00 +00:00
c7bd5740eb
hack to unbreak buildbots
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llvm-svn: 116461
2010-10-14 00:26:10 +00:00
698661c741
add uadd_ov/usub_ov to apint, consolidate constant folding
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logic to use the new APInt methods. Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold
which comes from "clang -ftrapv", originally brought to my attention from PR8221.
llvm-svn: 116457
2010-10-14 00:05:07 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
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and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
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llvm-svn: 116431
2010-10-13 20:58:46 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
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llvm-svn: 116421
2010-10-13 19:56:10 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
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llvm-svn: 116412
2010-10-13 18:00:52 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
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immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
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8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
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just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
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llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
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arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
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llvm-svn: 116383
2010-10-13 00:38:07 +00:00
f9ca535495
Refactor VCMP instructions.
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llvm-svn: 116379
2010-10-13 00:04:29 +00:00
a237bdbe52
FileCheckize this in a hope to quiet a valgrind warning on grep.
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llvm-svn: 116376
2010-10-12 23:47:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
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llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
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llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d5f8c3350d
Be nitpicky and line up the comments.
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llvm-svn: 116365
2010-10-12 23:14:03 +00:00
646a506724
Add encoding for VSUB and VCMP.
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Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
9513a7e87f
Don't need to specify calling convention. Add 'readnone' to functions.
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llvm-svn: 116354
2010-10-12 22:24:10 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
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llvm-svn: 116348
2010-10-12 22:08:41 +00:00
6fead930af
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
llvm-svn: 116313
2010-10-12 17:11:26 +00:00
65eb03ed6b
Add a simple testcase for tbaa.
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llvm-svn: 116272
2010-10-11 23:54:13 +00:00
b7c2962d20
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
llvm-svn: 116259
2010-10-11 23:16:21 +00:00
3e02306fed
PR8297
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llvm-svn: 116223
2010-10-11 21:08:42 +00:00
6c4353ecee
PowerPC varargs functions store live-in registers on the stack. Make sure we use
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virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.
This fixes PR8357.
llvm-svn: 116222
2010-10-11 20:43:09 +00:00
e2a0b6841a
Found a bug turning this on by default. Disable again for now.
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llvm-svn: 116220
2010-10-11 20:26:21 +00:00
6002b3b3e1
Remove now non-existent option.
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llvm-svn: 116219
2010-10-11 20:21:21 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
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llvm-svn: 116214
2010-10-11 19:02:04 +00:00
1ef5e84c31
Per discussion with Sanjiv, remove the PIC16 target from mainline. When/if
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it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.
llvm-svn: 116190
2010-10-11 05:44:40 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
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llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
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llvm-svn: 116174
2010-10-10 22:04:34 +00:00
f8f7537a77
force a triple, varargs isn't supported with the SVR4 ABI the buildbot tells me.
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llvm-svn: 116170
2010-10-10 18:59:01 +00:00
d10babfd65
fix the expansion of va_arg instruction on PPC to know the arg
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alignment for PPC32/64, avoiding some masking operations.
llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.
llvm-svn: 116168
2010-10-10 18:34:00 +00:00
b8d7efe785
Now using a variant of the existing inlining heuristics to decide whether to create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization.
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llvm-svn: 116158
2010-10-09 22:06:36 +00:00
a6a984bd96
MC-COFF: Fix .bss section size. Fixes PR8335. Patch by NAKAMUTA Takumi!
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llvm-svn: 116155
2010-10-09 16:04:45 +00:00
b20b08f898
Don't test a removed function.
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llvm-svn: 116154
2010-10-09 15:53:25 +00:00
86bbd71088
MC-COFF: Implement InitSections. Fixes PR8335.
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llvm-svn: 116151
2010-10-09 15:44:27 +00:00
c8dbdfd4ba
MC-COFF: Add COFFAsmParser. Completes PR8343.
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llvm-svn: 116150
2010-10-09 11:01:07 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
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1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
Wesley Peck