52d436e98b
rename test.
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llvm-svn: 76197
2009-07-17 18:05:55 +00:00
520024b465
Testcase for PR4214.
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llvm-svn: 76174
2009-07-17 11:44:20 +00:00
97f3f965eb
Make promotion in operation legalization for SETCC work correctly.
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llvm-svn: 76153
2009-07-17 05:16:04 +00:00
c5df7e2dc1
Emit cross regclass register moves for thumb2.
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Minor code duplication cleanup.
llvm-svn: 76124
2009-07-16 23:26:06 +00:00
c4148c4ec7
Assume an inline asm might be a call, so we get
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stack alignment right when it is. This is not
ideal but conservatively correct. Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c
llvm-svn: 76120
2009-07-16 22:34:45 +00:00
de9cd44ed8
Emit line numbers in asm comments when available.
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llvm-svn: 76117
2009-07-16 22:24:20 +00:00
070fab8a1f
Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.
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The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.
llvm-svn: 76101
2009-07-16 20:58:34 +00:00
357645efad
Changed my mind. We now allow remat of instructions whose defs have subreg indices.
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llvm-svn: 76100
2009-07-16 20:15:00 +00:00
bf61e3b4d3
this should be xfailed on darwin. Darwin doesn't use the libstdc++ in the llvm-gcc distro, it uses the system version.
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llvm-svn: 76095
2009-07-16 18:45:51 +00:00
fdd0eb4011
With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction.
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llvm-svn: 76094
2009-07-16 18:44:05 +00:00
8c129d7687
Fill in some holes in ScalarEvolution's loop iteration condition
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analysis. This allows indvars to emit a simpler loop trip count
expression.
llvm-svn: 76085
2009-07-16 17:34:36 +00:00
77a50bd3a8
Make xfail proper
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llvm-svn: 76065
2009-07-16 14:53:47 +00:00
73fcd3d962
Temporary disable 16 bit bswap
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llvm-svn: 76063
2009-07-16 14:35:57 +00:00
902facfe96
Add bswap patterns
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llvm-svn: 76061
2009-07-16 14:34:52 +00:00
3ae30e08ef
Fix logic inversion for RI-mode address selection
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llvm-svn: 76052
2009-07-16 14:31:14 +00:00
6c2c47ecb2
Unbreak the test
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llvm-svn: 76051
2009-07-16 14:30:49 +00:00
4121039bef
Expand 32-bit bitconverts via memory
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llvm-svn: 76050
2009-07-16 14:30:29 +00:00
bc2ead6ea3
Fix incomin arg stack frame offset in case we need to generate stack frame
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llvm-svn: 76049
2009-07-16 14:29:57 +00:00
bd41c83ab0
Revert the commit, it just hides the real bug
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llvm-svn: 76045
2009-07-16 14:28:26 +00:00
2acdac0f8e
Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects
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llvm-svn: 76035
2009-07-16 14:24:41 +00:00
b25949b0f5
Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
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llvm-svn: 76011
2009-07-16 14:18:17 +00:00
091872cb37
Implement 'large' PIC model
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llvm-svn: 76006
2009-07-16 14:16:05 +00:00
569a94c4d0
Implement shifts properly (hopefilly - finally!)
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llvm-svn: 76005
2009-07-16 14:15:24 +00:00
fe8df8ff61
Properly handle divides. As a bonus - implement memory versions of them.
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llvm-svn: 76003
2009-07-16 14:14:33 +00:00
34ad780d0d
32 bit shifts have only 12 bit displacements
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llvm-svn: 76000
2009-07-16 14:13:24 +00:00
1eb6262b4b
Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
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llvm-svn: 75990
2009-07-16 14:10:17 +00:00
62f8515b1c
Add support for 12 bit displacements
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llvm-svn: 75988
2009-07-16 14:09:35 +00:00
43d33bd6d2
Emit proper lowering of load from arg stack slot
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llvm-svn: 75986
2009-07-16 14:08:42 +00:00
a8197bb651
Implement dynamic allocas
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llvm-svn: 75985
2009-07-16 14:08:15 +00:00
7193e2670e
Add jump tables
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llvm-svn: 75984
2009-07-16 14:07:50 +00:00
2ff298fad0
Add rotates
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llvm-svn: 75981
2009-07-16 14:06:49 +00:00
9362d9aa76
Add patterns for integer negate
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llvm-svn: 75980
2009-07-16 14:06:27 +00:00
f07c7941f0
Provide proper patterns for and with imm instructions. Tune the tests accordingly.
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llvm-svn: 75979
2009-07-16 14:06:00 +00:00
59049d9176
Add 32 bit and reg-imm and disable invalid patterns for now
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llvm-svn: 75978
2009-07-16 14:05:32 +00:00
2d218394c6
Add z9 and z10 target processors. Mark z10-only instructions as such.
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llvm-svn: 75977
2009-07-16 14:05:00 +00:00
d568f6dce2
Proper lower 'small' results
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llvm-svn: 75962
2009-07-16 13:58:24 +00:00
f1bf3176c6
Completel forgot about unconditional branches
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llvm-svn: 75961
2009-07-16 13:57:52 +00:00
15d6e8785b
Lower addresses of globals
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llvm-svn: 75960
2009-07-16 13:57:27 +00:00
a442cdfb04
Test (incomplete) for easy muls
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llvm-svn: 75959
2009-07-16 13:57:03 +00:00
f0d7d6ce65
Provide "wide" muls and divs/rems
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llvm-svn: 75958
2009-07-16 13:56:42 +00:00
b04a4fa5c1
Tests for cmp / br_cc / select_cc
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llvm-svn: 75949
2009-07-16 13:53:15 +00:00
8695a30066
Emit callee-saved regs spills / restores
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llvm-svn: 75943
2009-07-16 13:51:12 +00:00
d694b9ff8b
Some preliminary call lowering
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llvm-svn: 75941
2009-07-16 13:50:21 +00:00
018599fc0b
Prologue / epilogue emission
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llvm-svn: 75940
2009-07-16 13:49:49 +00:00
09890bd434
Add simple frame index elimination
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llvm-svn: 75939
2009-07-16 13:49:25 +00:00
5dc5629100
Provide proper test :)
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llvm-svn: 75938
2009-07-16 13:48:59 +00:00
405833dfb6
Add address computation stuff
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llvm-svn: 75935
2009-07-16 13:47:59 +00:00
df99232d27
Add mem-imm stores
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llvm-svn: 75933
2009-07-16 13:47:14 +00:00
44f8bbfb3f
Add stores and truncstores
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llvm-svn: 75931
2009-07-16 13:45:00 +00:00
11b91b4e2e
Add patterns for various extloads
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llvm-svn: 75930
2009-07-16 13:44:30 +00:00
Chris Lattner