replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
117,679 Commits 2 Branches 0 Tags 1.8 GiB
Commit Graph

85 Commits

Author SHA1 Message Date
Jim Grosbach ae9132207f Better fix for ARM MOVT relocation encoding of thumb bit. 
Replaces r145318 with a more targetted fix for the relocation handling.

llvm-svn: 145346
 2011-11-29 01:15:25 +00:00
Jim Grosbach d3f02cbce9 Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
 2011-11-16 22:48:37 +00:00
Jim Grosbach 7ccdb7c0ae Fix encoding of NOP used for padding in ARM mode .align. 
llvm-svn: 144842
 2011-11-16 22:40:25 +00:00
Evan Cheng ecb2908bf9 Sink codegen optimization level into MCCodeGenInfo along side relocation model 
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
 2011-11-16 08:38:26 +00:00
Daniel Dunbar 52823cc91c build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

llvm-svn: 144444
 2011-11-12 02:10:57 +00:00
Daniel Dunbar bf9bba47a1 build: Add initial cut at LLVMBuild.txt files. 
llvm-svn: 143634
 2011-11-03 18:53:17 +00:00
Jim Grosbach fb2f1d61f4 ARM VLD/VST assembly parsing for symbolic address operands. 
llvm-svn: 143413
 2011-11-01 01:24:45 +00:00
David Meyer 49045ddb4c Remove NaClMode 
llvm-svn: 142338
 2011-10-18 05:29:23 +00:00
Jim Grosbach 69e6f90eb2 Tidy up. 80 columns. 
llvm-svn: 141043
 2011-10-03 23:03:26 +00:00
Jim Grosbach d76f43e18c Correct for my over-eager delete finger. 
llvm-svn: 140892
 2011-09-30 22:02:45 +00:00
Jim Grosbach 4e0dbee62b ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863
 2011-09-30 17:41:35 +00:00
Jim Grosbach d2222c386c ARM Fixup valus for movt/movw are for the whole value. 
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.

rdar://9653509

llvm-svn: 140861
 2011-09-30 17:23:05 +00:00
Jim Grosbach efc761a1eb ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
James Molloy 21efa7d6e1 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00
Ted Kremenek e3e36f80f5 Unbreak CMake build. 
llvm-svn: 140655
 2011-09-27 23:29:59 +00:00
Jim Grosbach 521526845c ARMv7a has the PKH instructions. 
llvm-svn: 139753
 2011-09-14 23:16:34 +00:00
Owen Anderson c3c60a0882 Fix encoding of Thumb2 shifted register operands with RRX shifts. 
llvm-svn: 139606
 2011-09-13 17:34:32 +00:00
Eli Friedman 12ea1b72a4 Zap some junk from the ARM instruction descriptions. 
llvm-svn: 139575
 2011-09-13 02:29:58 +00:00
Owen Anderson 4a9eb5f8dc Fix encoding of PC-relative LDRSHW with an immediate offset. 
llvm-svn: 139537
 2011-09-12 20:36:51 +00:00
Owen Anderson 5bfb0e0a85 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
llvm-svn: 139422
 2011-09-09 22:24:36 +00:00
Jim Grosbach a05627ebaf Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Jim Grosbach 7db8d697cf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
James Molloy 4c493e8050 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
llvm-svn: 139237
 2011-09-07 17:24:38 +00:00
Nick Lewycky 73df7e3830 Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain 
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!

llvm-svn: 139125
 2011-09-05 21:51:43 +00:00
Nick Lewycky f1a5f57d2f Fix typo in comment. 
llvm-svn: 139122
 2011-09-05 18:35:03 +00:00
Benjamin Kramer 6397051ece Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
 2011-09-01 23:04:27 +00:00
Owen Anderson a455a0b1e7 Fix encoding for tBcc with immediate offset operand. 
llvm-svn: 138889
 2011-08-31 20:26:14 +00:00
Owen Anderson 5c160fd243 Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
llvm-svn: 138874
 2011-08-31 18:30:20 +00:00
Owen Anderson fdf3cd7f2b Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
llvm-svn: 138837
 2011-08-30 22:15:17 +00:00
Owen Anderson d16fb43b1f Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
llvm-svn: 138835
 2011-08-30 22:10:03 +00:00
Owen Anderson 543c89fb15 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
llvm-svn: 138834
 2011-08-30 22:03:20 +00:00
Owen Anderson 1732c2ebf6 Clean up whitespace. 
llvm-svn: 138833
 2011-08-30 21:58:18 +00:00
Owen Anderson 967674d26c Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00
Owen Anderson b205c029a4 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Owen Anderson 6c70e58041 Correct encoding of BL with immediate offset. 
llvm-svn: 138673
 2011-08-26 22:54:51 +00:00
Owen Anderson a01bcbfc80 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
llvm-svn: 138635
 2011-08-26 18:09:22 +00:00
Jim Grosbach 21a60b6f90 ARM asm backend initialize isThumbMode based on target triple. 
llvm-svn: 138501
 2011-08-24 22:27:35 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Evan Cheng 4d6c9d711d Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.

llvm-svn: 138367
 2011-08-23 20:15:21 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal). 
llvm-svn: 138052
 2011-08-19 18:20:48 +00:00
Jim Grosbach f00b9ccd22 ARM Thumb blx instruction fixup has same data range as bl. 
These fixups are handled poorly in general, and should have a single
contiguous range of bits per fixup type, but that's not how they're
currently organized, so for now in complex ones like for blx, we just tell the
emitter it's OK for the fixup to munge any bit it wants.

llvm-svn: 137947
 2011-08-18 16:57:50 +00:00
Jim Grosbach 46dd413991 ARM clean up the imm_sr operand class representation. 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
 2011-08-17 21:51:27 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
 2011-08-16 17:06:20 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
llvm-svn: 137322
 2011-08-11 18:41:59 +00:00
Benjamin Kramer de2c381331 The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore. 
llvm-svn: 137151
 2011-08-09 21:34:19 +00:00
Owen Anderson c40303885b Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0. 
llvm-svn: 137062
 2011-08-08 20:42:17 +00:00
Benjamin Kramer c22d50e5c3 Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions. 
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.

llvm-svn: 137059
 2011-08-08 18:56:44 +00:00
Jim Grosbach a70fbfd577 ARM simplify the postidx_reg operand encoding. 
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
 2011-08-05 16:11:38 +00:00