Commit Graph

27 Commits

Author SHA1 Message Date
Evan Cheng b8b0ad80a8 Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905
2011-01-20 08:34:58 +00:00
Evan Cheng 79ff5238e9 Conditional moves are slightly more expensive than moves.
llvm-svn: 118985
2010-11-13 05:14:20 +00:00
Andrew Trick f4ebec03e0 putback r116983 and fix simple-fp-encoding.ll tests
llvm-svn: 116992
2010-10-21 03:40:16 +00:00
Owen Anderson 9e00f27e14 Revert r116983, which is breaking all the buildbots.
llvm-svn: 116987
2010-10-21 03:11:16 +00:00
Evan Cheng 15c2ac90ec Add missing scheduling itineraries for transfers between core registers and VFP registers.
llvm-svn: 116983
2010-10-21 01:12:00 +00:00
Evan Cheng 1958cefd69 Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
Evan Cheng 49d4c0bd18 - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.

llvm-svn: 115755
2010-10-06 06:27:31 +00:00
Evan Cheng 2fb20b1d37 ARM instruction itinerary fixes:
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121
2010-09-30 01:08:25 +00:00
Evan Cheng 2259d67a33 Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
llvm-svn: 115010
2010-09-29 00:49:25 +00:00
Evan Cheng c35d7bbe43 Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
llvm-svn: 115008
2010-09-29 00:27:46 +00:00
Evan Cheng 0097dd0d5a Add support to model pipeline bypass / forwarding.
llvm-svn: 115005
2010-09-28 23:50:49 +00:00
Evan Cheng 8f9a2244fc Remove a unused instruction itinerary class.
llvm-svn: 114782
2010-09-25 01:06:02 +00:00
Evan Cheng 62d626ce86 Fix zero and sign extension instructions scheduling itineraries.
llvm-svn: 114780
2010-09-25 00:49:35 +00:00
Evan Cheng e37da03e60 More pseudo instruction scheduling itinerary fixes.
llvm-svn: 114768
2010-09-24 22:41:41 +00:00
Evan Cheng 367a5df8cf For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513
2010-09-09 18:18:55 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change.
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
Anton Korobeynikov 7d62e33291 Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
2010-04-18 20:31:01 +00:00
David Goodwin 1fd5fdaa7b Add ARMv6 itineraries.
llvm-svn: 89218
2009-11-18 18:39:57 +00:00
David Goodwin afcaf79603 Checkpoint NEON scheduling itineraries.
llvm-svn: 82657
2009-09-23 21:38:08 +00:00
David Goodwin 5090273367 Add Cortex-A8 VFP model.
llvm-svn: 82483
2009-09-21 20:52:17 +00:00
David Goodwin a7c2dfbca1 Update Cortex-A8 instruction itineraries for integer instructions.
llvm-svn: 79436
2009-08-19 18:00:44 +00:00
Evan Cheng 6ddd7bcdd1 Turn on if-conversion for thumb2.
llvm-svn: 79084
2009-08-15 07:59:10 +00:00
David Goodwin a9c2aad939 Finalize itineraries for cortex-a8 integer multiply
llvm-svn: 78908
2009-08-13 15:51:13 +00:00
David Goodwin fd5defed1d Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
llvm-svn: 78736
2009-08-11 22:38:43 +00:00
David Goodwin 62e053b790 Checkpoint scheduling itinerary changes.
llvm-svn: 78564
2009-08-10 15:56:13 +00:00
Evan Cheng f206d925a5 Fix comment.
llvm-svn: 76693
2009-07-21 23:54:22 +00:00
Evan Cheng 4e712de541 Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
llvm-svn: 73747
2009-06-19 01:51:50 +00:00