d20628ff7d
Pattern match bitfield insert, which helps shift long by immediate, among
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other things.
llvm-svn: 21127
2005-04-06 23:51:40 +00:00
505f6b760d
Fix some shift bugs
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llvm-svn: 21126
2005-04-06 22:42:08 +00:00
39ef2f1d43
Fixed version of optimized integer divide is now fixed. Calculate the
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quotient, not the remainder. Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.
llvm-svn: 21111
2005-04-06 06:44:57 +00:00
dd397119b0
Turn off the div -> mul optimization until it works correctly 100% of the
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time.
llvm-svn: 21105
2005-04-06 03:36:33 +00:00
4164c4baac
Add support for MULHS and MULHU nodes
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Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
llvm-svn: 21104
2005-04-06 00:25:27 +00:00
524417357c
Behold, rlwinm with certain immediate arguments is printed as the much more
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readable slwi or srwi (shift left/right word immediate).
llvm-svn: 21099
2005-04-05 18:19:50 +00:00
a188b698a2
Fix cut & paste errors (32->64), and codegen float->int more optimally.
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llvm-svn: 21098
2005-04-05 17:32:30 +00:00
9203e169a7
Remove 64 bit simple ISel, it never worked correctly
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Add initial (buggy) implementation of 64 bit pattern ISel
llvm-svn: 21096
2005-04-05 08:51:15 +00:00
4bde071216
Back out the previous change to SelectBranchCC, since there are cases it
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could miscompile. A correct solution will be found in the near future.
llvm-svn: 21095
2005-04-05 04:32:16 +00:00
9049e4beec
Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better
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indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.
llvm-svn: 21094
2005-04-05 04:22:58 +00:00
d6933f5078
Implement SDIV by power of 2 as srawi/addze rather than load imm, divw
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llvm-svn: 21091
2005-04-05 00:15:08 +00:00
1d5d767a09
Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub
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llvm-svn: 21090
2005-04-04 23:40:36 +00:00
d96350095c
Add support for multiply-add, multiply-sub, and their negated versions
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llvm-svn: 21089
2005-04-04 23:01:51 +00:00
1194531057
Make sure that arg regs used by the call instruction are marked as such, so
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that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.
llvm-svn: 21086
2005-04-04 22:17:48 +00:00
c7186025de
Remove unnecessary register copy now that regalloc is fixed
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llvm-svn: 21085
2005-04-04 21:48:13 +00:00
d753765460
i1 loads should also be from the low byte of the argument word.
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llvm-svn: 21077
2005-04-04 09:09:00 +00:00
1ce4839890
Fix i64 return, fix CopyFromReg
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llvm-svn: 21076
2005-04-04 06:52:38 +00:00
629cdaea39
Full varargs support. All of UnitTests now passes
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llvm-svn: 21070
2005-04-03 23:11:17 +00:00
7a3e929efc
Pass the correct value for the chain to the store
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llvm-svn: 21066
2005-04-03 22:22:56 +00:00
f6dc43bd46
Fix SHL_PARTS
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Start implementation of integer varargs
llvm-svn: 21065
2005-04-03 22:13:27 +00:00
34cc5b329f
Keeping up with the Joneses.
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Implement not, nor, nand, and eqv
llvm-svn: 21060
2005-04-03 11:20:20 +00:00
165cf4844e
Set shift amount to Extend
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Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions
llvm-svn: 21018
2005-04-02 05:59:34 +00:00
0b7e4cd107
This target doesn't support fabs/fneg yet.
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llvm-svn: 21010
2005-04-02 05:03:24 +00:00
cfc452d088
Fix i64 returns
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Generate PowerPC 'subfic' instruction when appropriate
llvm-svn: 20995
2005-04-02 00:42:16 +00:00
cda9aa7fa9
Add ISD::UNDEF node
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Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
arguments, but not shadowing their value. This allows us to do the right
thing with both fixed and vararg floating point arguments.
llvm-svn: 20988
2005-04-01 22:34:39 +00:00
1c3aea6019
Fix Olden/bh, CR0 was being set in the wrong order
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LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.
llvm-svn: 20981
2005-04-01 08:57:43 +00:00
c9e50238c5
Also apply Chris's fix to FP select and SETCC
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llvm-svn: 20979
2005-04-01 07:21:30 +00:00
ffc7f243fe
Move the selection of the arms of the select operation up to the conditional
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part to make sure we get the side effects and to avoid confusing the CFG.
llvm-svn: 20977
2005-04-01 07:10:02 +00:00
2095f3b06b
Fix stores to global addresses
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Fix calls with no arguments
llvm-svn: 20975
2005-04-01 05:57:17 +00:00
839b34c367
Support indexed loads and stores. This drops Shootout/matrix time from
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18.8 to 14.8 seconds. The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.
llvm-svn: 20973
2005-04-01 04:45:11 +00:00
f4d91610ff
Implement FP_TO_SINT and FP_TO_UINT
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llvm-svn: 20972
2005-04-01 02:59:27 +00:00
508aac2ca8
Add support for adding 0.0 and -0.0 to the constant pool, since we lie and
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say that we support them, for the purposes of generating fsel instructions.
llvm-svn: 20970
2005-04-01 01:08:07 +00:00
4f3a9860d3
Factor out common code, support FP comparison in folded SetCC
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llvm-svn: 20969
2005-04-01 00:32:34 +00:00
6215b35918
fsel generation for f32 and f64 select
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generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select
Code generation quality for Shootout is now on par with the Simple ISel
llvm-svn: 20968
2005-03-31 23:55:40 +00:00
eddfff338a
Pass the correct values to the chain argument for node construction during
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LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!
llvm-svn: 20946
2005-03-31 02:05:53 +00:00
9de7ddf7d5
Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs
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Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads
As a result, all of Shootout, and likely many other programs are now
working.
llvm-svn: 20945
2005-03-31 00:15:26 +00:00
4c0780cf42
Fix calls whose arguments fit entirely in registers to not break the Chain.
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Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel
llvm-svn: 20944
2005-03-30 19:38:35 +00:00
a8114a0f48
Fix frame index code to generate legal PowerPC instructions. About half of
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Shootout now works.
llvm-svn: 20940
2005-03-30 02:23:08 +00:00
5851a66128
Fix external symbol printing in the AsmPrinter. Tell the ISel that we
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don't support things like memcpy directly. This allows a handful of the
Shootout programs to work, yay!
llvm-svn: 20939
2005-03-30 01:45:43 +00:00
9c40e9c61f
Fix BranchCC (it's still dumb), and implement FP select (also dumb)
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llvm-svn: 20935
2005-03-29 22:48:55 +00:00
28145edd30
Implement integer select and i1 sign extend
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llvm-svn: 20934
2005-03-29 22:24:51 +00:00
28c5ac9ff4
Implement SetCC, fix ZERO_EXTEND_INREG
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llvm-svn: 20933
2005-03-29 21:54:38 +00:00
1ce9aacf2e
fix a warning in the optimized build
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llvm-svn: 20920
2005-03-29 15:13:27 +00:00
60956dd52f
Implement div, rem, and frameindex
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llvm-svn: 20907
2005-03-29 00:03:27 +00:00
731bed10c7
Pattern ISel: fix argument loading for i64s (thanks chris)
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Simple ISel: fix i64 subtract
llvm-svn: 20903
2005-03-28 23:08:54 +00:00
66acad746f
Remove fake instruction 'subc' (mnemonic for subfc).
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More pattern isel updates
llvm-svn: 20902
2005-03-28 22:28:37 +00:00
5bdfc63516
Implement proper loads and zero-extends of all types
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llvm-svn: 20897
2005-03-28 19:36:43 +00:00
518a994b7d
Fix that pesky floats in integer regs problem by assigning the f32 type to
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the correct register class. Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.
llvm-svn: 20857
2005-03-26 08:25:22 +00:00
dcad53e7bd
Get closer to having varargs working. There's still something strange
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going on with copies between floating point and integer register files
being generated. Once that is solved, varargs will be done.
llvm-svn: 20856
2005-03-26 07:46:36 +00:00
c95bf7b226
Make 64bit args and float args work correct with calls. Thanks to Chris
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for explaining EXTRACT_ELEMENT to me.
llvm-svn: 20847
2005-03-26 02:17:46 +00:00
Nate Begeman