8bff8a1e87
Fix a TargetLowering optimization so that it doesn't duplicate
...
loads when an input node has multiple uses.
llvm-svn: 68398
2009-04-03 20:11:30 +00:00
b425feb2aa
Delete ISD::INSERT_SUBREG and ISD::EXTRACT_SUBREG, which are unused.
...
Note that these are distinct from TargetInstrInfo::INSERT_SUBREG
and TargetInstrInfo::EXTRACT_SUBREG, which are used.
llvm-svn: 68355
2009-04-03 00:25:26 +00:00
cc841a3810
To convert the StopPoint insn into an assembler directive by ISel, we need to have access to the line number field. So we convert that info as an operand by custom handling DBG_STOPPOINT in legalize.
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llvm-svn: 68329
2009-04-02 18:03:10 +00:00
0d551591ea
Fully general expansion of integer shift of any size.
...
llvm-svn: 68134
2009-03-31 19:39:24 +00:00
6b42dfddf4
Reapply 68073, with fixes. EH Landing-pad basic blocks are not
...
entered via fall-through. Don't miss fallthroughs from blocks
terminated by conditional branches. Also, move
isOnlyReachableByFallthrough out of line.
llvm-svn: 68129
2009-03-31 18:39:13 +00:00
d51f196ff5
Minor top-level comment fix.
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llvm-svn: 68113
2009-03-31 16:51:18 +00:00
b8017e02ca
Oy! When reverting r68073, I added in experimental code. Sorry...
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llvm-svn: 68099
2009-03-31 08:41:31 +00:00
4486c1fac0
Remove the "fast" cases for spill and restore point determination, as these were subtlely wrong in obscure cases. Patch the testcase
...
to account for this change.
llvm-svn: 68093
2009-03-31 08:27:09 +00:00
c4b08e5eb0
Revert r68073. It's causing a failure in the Apple-style builds.
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llvm-svn: 68092
2009-03-31 08:26:26 +00:00
97a20b8dbf
Fix live-out reg logic to not insert over-aggressive AssertZExt
...
instructions. This fixes lua.
llvm-svn: 68083
2009-03-31 01:38:29 +00:00
09f5be8146
Turn a 2-address instruction into a 3-address one when it's profitable even if the two-address operand is killed.
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e.g.
%reg1024<def> = MOV r1
%reg1025<def> = ADD %reg1024, %reg1026
r0 = MOV %reg1025
If it's not possible / profitable to commute ADD, then turning ADD into a LEA saves a copy.
llvm-svn: 68065
2009-03-30 21:34:07 +00:00
2f52e6488f
Balance out quote in debug output.
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llvm-svn: 68059
2009-03-30 20:32:22 +00:00
5f0d97c571
Fix grammar-o in comment.
...
llvm-svn: 68057
2009-03-30 20:30:02 +00:00
ff62c62b7c
Constify arguments in isSuccessor and isLayoutSuccessor.
...
llvm-svn: 68054
2009-03-30 20:06:29 +00:00
d21581eaa1
Fix PR3899: add support for extracting floats from vectors
...
when using -soft-float.
Based on a patch by Jakob Stoklund Olesen.
llvm-svn: 67996
2009-03-29 13:51:06 +00:00
e622cbf385
Make check in CheckTailCallReturnConstraints for ignorable instructions between
...
a CALL and a RET node more generic. Add a test for tail calls with a void
return.
llvm-svn: 67943
2009-03-28 12:36:29 +00:00
83d5420d02
Enable tail call optimization for functions that return a struct (bug 3664) and for functions that return types that need extending (e.g i1).
...
llvm-svn: 67934
2009-03-28 08:33:27 +00:00
fd81c73cde
Optimize some 64-bit multiplication by constants into two lea's or one lea + shl since imulq is slow (latency 5). e.g.
...
x * 40
=>
shlq $3, %rdi
leaq (%rdi,%rdi,4), %rax
This has the added benefit of allowing more multiply to be folded into addressing mode. e.g.
a * 24 + b
=>
leaq (%rdi,%rdi,2), %rax
leaq (%rsi,%rax,8), %rax
llvm-svn: 67917
2009-03-28 05:57:29 +00:00
2785e4be37
Fix what surely must be a copy+pasto.
...
llvm-svn: 67881
2009-03-27 23:55:04 +00:00
6d75876473
Initialize LiveOutInfo's APInt members to zero, as APInt's
...
default constructor produces an uninitialized APInt.
This fixes PR3896.
llvm-svn: 67879
2009-03-27 23:51:02 +00:00
a1be2dcd63
Shrink wrapping in PEI: initial release. Finishing development, enable with --shrink-wrap.
...
llvm-svn: 67828
2009-03-27 06:09:40 +00:00
76a561f35e
Don't assign a new stack slot if the pre-alloc splitter already assigned one.
...
llvm-svn: 67764
2009-03-26 18:53:38 +00:00
aa28be652c
Pull transform from target-dependent code into target-independent code.
...
llvm-svn: 67742
2009-03-26 06:14:09 +00:00
2e9f42bed5
Revert 67132. This is breaking some objective-c apps.
...
Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext.
llvm-svn: 67701
2009-03-25 20:20:11 +00:00
eb1646d28c
When optimizing with debug info, don't keep the
...
stoppoint nodes around until Legalize; doing this
imposed an ordering on a sequence of loads that
came from different lines, interfering with scheduling.
llvm-svn: 67692
2009-03-25 17:36:08 +00:00
5e5a63cf8f
CodeGen still defaults to non-verbose asm, but llc now overrides it and default to verbose.
...
llvm-svn: 67668
2009-03-25 01:47:28 +00:00
a6e85a19c6
Do not ignore DW_TAG_class_type!
...
llvm-svn: 67661
2009-03-25 00:28:40 +00:00
f413a88839
Fix PR3845: Avoid stale MachineInstruction pointer reference.
...
llvm-svn: 67649
2009-03-24 20:33:17 +00:00
c35847e109
more tidying: name the components of PhysReg in the case when
...
the target constraint specifies a specific physreg.
llvm-svn: 67618
2009-03-24 15:27:37 +00:00
42eceb3491
Tidy a bit more.
...
llvm-svn: 67617
2009-03-24 15:25:07 +00:00
246eda43bd
simplify this code a bit now that "allocation to a vreg class" can never
...
fail.
llvm-svn: 67616
2009-03-24 15:22:11 +00:00
f3746cbc56
Minor compile-time optimization; don't bother checking
...
canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.
llvm-svn: 67587
2009-03-24 00:50:07 +00:00
9a658d72db
Add a pre-pass to the burr-list scheduler which makes adjustments to
...
help out the register pressure reduction heuristics in the case of
nodes with multiple uses. Currently this uses very conservative
heuristics, so it doesn't have a broad impact, but in cases where it
does help it can make a big difference.
llvm-svn: 67586
2009-03-24 00:49:12 +00:00
a774a99245
Do not emit comments unless -asm-verbose.
...
llvm-svn: 67580
2009-03-24 00:17:40 +00:00
7fe1b0f50f
Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases.
...
e.g. allocating for GR32, bh is not used, updating bl spill weight.
bl should get the same spill weight otherwise it will be choosen
as a spill candidate since spilling bh doesn't make ebx available.
This fix PR2866.
llvm-svn: 67574
2009-03-23 22:57:19 +00:00
93eefa0043
Fix internal representation of fp80 to be the
...
same as a normal i80 {low64, high16} rather
than its own {high64, low16}. A depressing number
of places know about this; I think I got them all.
Bitcode readers and writers convert back to the old
form to avoid breaking compatibility.
llvm-svn: 67562
2009-03-23 21:16:53 +00:00
ed0e8d44ce
When unfolding a load during scheduling, the new operator node has
...
a data dependency on the load node, so it really needs a
data-dependence edge to the load node, even if the load previously
existed.
And add a few comments.
llvm-svn: 67554
2009-03-23 20:20:43 +00:00
f858466018
Fix PR3391 and PR3864. Reg allocator infinite looping.
...
llvm-svn: 67544
2009-03-23 18:24:37 +00:00
f477262e69
Don't set SUnit::hasPhysRegDefs to true unless the defs are
...
actually have uses, which reflects the way it's used.
llvm-svn: 67540
2009-03-23 17:39:36 +00:00
a366da1bf7
Fix canClobberPhysRegDefs to check all SDNodes grouped together
...
in an SUnit, instead of just the first one. This fix is needed
by some upcoming scheduler changes.
llvm-svn: 67531
2009-03-23 16:23:01 +00:00
52c278e54d
Add a new bit to SUnit to record whether a node has implicit physreg
...
defs, regardless of whether they are actually used.
llvm-svn: 67528
2009-03-23 16:10:52 +00:00
4f2fea1a21
Now that errs() is properly non-buffered, there's no need to
...
explicitly flush it.
llvm-svn: 67526
2009-03-23 15:57:19 +00:00
968c3b0d6e
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies.
...
llvm-svn: 67512
2009-03-23 08:01:15 +00:00
47c9750f04
Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
...
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.
llvm-svn: 67511
2009-03-23 07:19:58 +00:00
3bdc4bdba6
Simplify this code; use a while instead of an if and a do-while.
...
llvm-svn: 67400
2009-03-20 20:42:23 +00:00
2e55923fba
For inline asm output operand that matches an input. Encode the input operand index in the high bits.
...
llvm-svn: 67387
2009-03-20 18:03:34 +00:00
83debdf4b4
Fixed build warnings for unused variables.
...
llvm-svn: 67372
2009-03-20 13:49:20 +00:00
e9759c458c
Fixed the comment. No functionality change.
...
llvm-svn: 67370
2009-03-20 09:38:50 +00:00
f0db9b6321
Apply the patch requested in PR3846.
...
llvm-svn: 67364
2009-03-20 05:08:24 +00:00
8d5baa09f8
Fix the Win32 VS2008 build:
...
- Make type declarations match the struct/class keyword of the definition.
- Move AddSignalHandler into the namespace where it belongs.
- Correctly call functions from template base.
- Some other small changes.
With this patch, LLVM and Clang should build properly and with far less noise under VS2008.
llvm-svn: 67347
2009-03-19 23:26:52 +00:00
Dan Gohman