a2b8c3f98f
Forgot this test earlier.
...
llvm-svn: 76485
2009-07-20 21:46:42 +00:00
0ebd69614c
Assembly and Bitcode support for unsigned/signed overflow flags and
...
exact sdiv flags.
llvm-svn: 76475
2009-07-20 21:19:07 +00:00
57106d6dc0
Use TII->findCommutedOpIndices to find the commute operands (rather than guessing).
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llvm-svn: 76472
2009-07-20 21:16:08 +00:00
ee5513582d
Removed the DumpSymbolsandMacros and LoadSymbolsandMacros MCStreamer API as
...
the parsing of the .dump and .load should be done in the assembly parser and
not have any need for an MCStreamer API. Changed the code for now so these
just produce an error saying these specific directives are not yet implemented
since they are likely no longer used and may never need to be implemented.
llvm-svn: 76462
2009-07-20 20:25:37 +00:00
027d9f93ea
Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class.
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llvm-svn: 76458
2009-07-20 19:47:55 +00:00
33a3fd0b9c
Revert the addition of hasNoPointerOverflow to GEPOperator.
...
Getelementptrs that are defined to wrap are virtually useless to
optimization, and getelementptrs that are undefined on any kind
of overflow are too restrictive -- it's difficult to ensure that
all intermediate addresses are within bounds. I'm going to take
a different approach.
Remove a few optimizations that depended on this flag.
llvm-svn: 76437
2009-07-20 17:43:30 +00:00
40ed0ae8ef
xfail for now.
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llvm-svn: 76423
2009-07-20 15:33:09 +00:00
58f9bb2ccd
implement a new magic global "llvm.compiler.used" which is like llvm.used, but
...
doesn't cause ".no_dead_strip" to be emitted on darwin.
llvm-svn: 76399
2009-07-20 06:14:25 +00:00
4e4eb0b00c
Restore AsmWriterEmitter.cpp back to 74742. The recent changes broke Thumb.
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llvm-svn: 76398
2009-07-20 06:10:07 +00:00
81d53960ad
This test should be run with -m32.
...
llvm-svn: 76382
2009-07-19 22:44:03 +00:00
aba695c7d0
Fix http://llvm.org/bugs/show_bug.cgi?id=4583
...
Inline asm instructions may have additional <imp-def,kill> register operands.
These operands are not marked with a flag like the normal asm operands, so we
must not assert that there is a flag.
llvm-svn: 76373
2009-07-19 19:09:59 +00:00
048e78fc5b
Canonicalize bitcasts between types like <1 x i64> and i64 to
...
insertelement/extractelement.
I'm not entirely sure this is precisely what we want to do: should we
prefer bitcast(insertelement) or insertelement(bitcast)? Similarly. should we
prefer extractelement(bitcast) or bitcast(extractelement)?
llvm-svn: 76345
2009-07-18 23:06:53 +00:00
eb6bcf3462
Back out 76300; apparently the preference is to canonicalize the other
...
way (bitcast -> insert/extractelement).
llvm-svn: 76325
2009-07-18 19:04:16 +00:00
52dbfc21c5
Add combine: X sdiv (1 << Y) -> X udiv (1 << Y) when X doesn't have the
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sign bit set.
llvm-svn: 76304
2009-07-18 09:53:21 +00:00
a807aae226
Canonicalize insert/extractelement from single-element vectors into
...
bitcasts.
It would also be possible to canonicalize the other way; does anyone
have a preference?
llvm-svn: 76300
2009-07-18 09:07:47 +00:00
ff9bf97ceb
Fix simplifylibcalls memset recognition to work on 64-bit platforms
...
where int is 32 bits.
llvm-svn: 76293
2009-07-18 08:34:51 +00:00
090db9b7a9
Catch more coalescing opportunities.
...
llvm-svn: 76282
2009-07-18 04:52:23 +00:00
e20cbf3068
Enable cross register class coalescing.
...
llvm-svn: 76281
2009-07-18 02:10:10 +00:00
a776067d3f
Fix pr4552. Stack slot coloring with register must take care not to generate illegal ams.
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llvm-svn: 76258
2009-07-17 22:42:51 +00:00
8c6bad2f66
llvm-mc: Add -triple, and start fetching the target asm printer.
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llvm-svn: 76257
2009-07-17 22:38:58 +00:00
18fe458103
Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
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llvm-svn: 76248
2009-07-17 22:13:25 +00:00
52d436e98b
rename test.
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llvm-svn: 76197
2009-07-17 18:05:55 +00:00
520024b465
Testcase for PR4214.
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llvm-svn: 76174
2009-07-17 11:44:20 +00:00
97f3f965eb
Make promotion in operation legalization for SETCC work correctly.
...
llvm-svn: 76153
2009-07-17 05:16:04 +00:00
c5df7e2dc1
Emit cross regclass register moves for thumb2.
...
Minor code duplication cleanup.
llvm-svn: 76124
2009-07-16 23:26:06 +00:00
c4148c4ec7
Assume an inline asm might be a call, so we get
...
stack alignment right when it is. This is not
ideal but conservatively correct. Adjust a test
to compensate for changed stack offset value.
gcc.apple/asm-block-57.c
llvm-svn: 76120
2009-07-16 22:34:45 +00:00
de9cd44ed8
Emit line numbers in asm comments when available.
...
llvm-svn: 76117
2009-07-16 22:24:20 +00:00
070fab8a1f
Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.
...
The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.
llvm-svn: 76101
2009-07-16 20:58:34 +00:00
357645efad
Changed my mind. We now allow remat of instructions whose defs have subreg indices.
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llvm-svn: 76100
2009-07-16 20:15:00 +00:00
bf61e3b4d3
this should be xfailed on darwin. Darwin doesn't use the libstdc++ in the llvm-gcc distro, it uses the system version.
...
llvm-svn: 76095
2009-07-16 18:45:51 +00:00
fdd0eb4011
With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction.
...
llvm-svn: 76094
2009-07-16 18:44:05 +00:00
8c129d7687
Fill in some holes in ScalarEvolution's loop iteration condition
...
analysis. This allows indvars to emit a simpler loop trip count
expression.
llvm-svn: 76085
2009-07-16 17:34:36 +00:00
77a50bd3a8
Make xfail proper
...
llvm-svn: 76065
2009-07-16 14:53:47 +00:00
73fcd3d962
Temporary disable 16 bit bswap
...
llvm-svn: 76063
2009-07-16 14:35:57 +00:00
902facfe96
Add bswap patterns
...
llvm-svn: 76061
2009-07-16 14:34:52 +00:00
3ae30e08ef
Fix logic inversion for RI-mode address selection
...
llvm-svn: 76052
2009-07-16 14:31:14 +00:00
6c2c47ecb2
Unbreak the test
...
llvm-svn: 76051
2009-07-16 14:30:49 +00:00
4121039bef
Expand 32-bit bitconverts via memory
...
llvm-svn: 76050
2009-07-16 14:30:29 +00:00
bc2ead6ea3
Fix incomin arg stack frame offset in case we need to generate stack frame
...
llvm-svn: 76049
2009-07-16 14:29:57 +00:00
bd41c83ab0
Revert the commit, it just hides the real bug
...
llvm-svn: 76045
2009-07-16 14:28:26 +00:00
2acdac0f8e
Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects
...
llvm-svn: 76035
2009-07-16 14:24:41 +00:00
b25949b0f5
Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
...
llvm-svn: 76011
2009-07-16 14:18:17 +00:00
091872cb37
Implement 'large' PIC model
...
llvm-svn: 76006
2009-07-16 14:16:05 +00:00
569a94c4d0
Implement shifts properly (hopefilly - finally!)
...
llvm-svn: 76005
2009-07-16 14:15:24 +00:00
fe8df8ff61
Properly handle divides. As a bonus - implement memory versions of them.
...
llvm-svn: 76003
2009-07-16 14:14:33 +00:00
34ad780d0d
32 bit shifts have only 12 bit displacements
...
llvm-svn: 76000
2009-07-16 14:13:24 +00:00
1eb6262b4b
Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
...
llvm-svn: 75990
2009-07-16 14:10:17 +00:00
62f8515b1c
Add support for 12 bit displacements
...
llvm-svn: 75988
2009-07-16 14:09:35 +00:00
43d33bd6d2
Emit proper lowering of load from arg stack slot
...
llvm-svn: 75986
2009-07-16 14:08:42 +00:00
a8197bb651
Implement dynamic allocas
...
llvm-svn: 75985
2009-07-16 14:08:15 +00:00
7193e2670e
Add jump tables
...
llvm-svn: 75984
2009-07-16 14:07:50 +00:00
2ff298fad0
Add rotates
...
llvm-svn: 75981
2009-07-16 14:06:49 +00:00
9362d9aa76
Add patterns for integer negate
...
llvm-svn: 75980
2009-07-16 14:06:27 +00:00
f07c7941f0
Provide proper patterns for and with imm instructions. Tune the tests accordingly.
...
llvm-svn: 75979
2009-07-16 14:06:00 +00:00
59049d9176
Add 32 bit and reg-imm and disable invalid patterns for now
...
llvm-svn: 75978
2009-07-16 14:05:32 +00:00
2d218394c6
Add z9 and z10 target processors. Mark z10-only instructions as such.
...
llvm-svn: 75977
2009-07-16 14:05:00 +00:00
d568f6dce2
Proper lower 'small' results
...
llvm-svn: 75962
2009-07-16 13:58:24 +00:00
f1bf3176c6
Completel forgot about unconditional branches
...
llvm-svn: 75961
2009-07-16 13:57:52 +00:00
15d6e8785b
Lower addresses of globals
...
llvm-svn: 75960
2009-07-16 13:57:27 +00:00
a442cdfb04
Test (incomplete) for easy muls
...
llvm-svn: 75959
2009-07-16 13:57:03 +00:00
f0d7d6ce65
Provide "wide" muls and divs/rems
...
llvm-svn: 75958
2009-07-16 13:56:42 +00:00
b04a4fa5c1
Tests for cmp / br_cc / select_cc
...
llvm-svn: 75949
2009-07-16 13:53:15 +00:00
8695a30066
Emit callee-saved regs spills / restores
...
llvm-svn: 75943
2009-07-16 13:51:12 +00:00
d694b9ff8b
Some preliminary call lowering
...
llvm-svn: 75941
2009-07-16 13:50:21 +00:00
018599fc0b
Prologue / epilogue emission
...
llvm-svn: 75940
2009-07-16 13:49:49 +00:00
09890bd434
Add simple frame index elimination
...
llvm-svn: 75939
2009-07-16 13:49:25 +00:00
5dc5629100
Provide proper test :)
...
llvm-svn: 75938
2009-07-16 13:48:59 +00:00
405833dfb6
Add address computation stuff
...
llvm-svn: 75935
2009-07-16 13:47:59 +00:00
df99232d27
Add mem-imm stores
...
llvm-svn: 75933
2009-07-16 13:47:14 +00:00
44f8bbfb3f
Add stores and truncstores
...
llvm-svn: 75931
2009-07-16 13:45:00 +00:00
11b91b4e2e
Add patterns for various extloads
...
llvm-svn: 75930
2009-07-16 13:44:30 +00:00
04be818918
Add shifts and reg-imm address matching
...
llvm-svn: 75927
2009-07-16 13:43:18 +00:00
cf7ea6a94f
Add bunch of 32-bit patterns... Uffff :)
...
llvm-svn: 75926
2009-07-16 13:42:31 +00:00
5618d808e0
Add tests for fixes I committed earlier to the C++ FE.
...
llvm-svn: 75924
2009-07-16 13:35:42 +00:00
ebe2de0e14
Add bunch of reg-imm movs
...
llvm-svn: 75921
2009-07-16 13:34:50 +00:00
28234bcde2
Provide masked reg-imm 'or' and 'and'
...
llvm-svn: 75919
2009-07-16 13:33:57 +00:00
1c4c7823ae
Fix test running lines
...
llvm-svn: 75918
2009-07-16 13:33:21 +00:00
0d76b17a78
Add reg-reg and pattern
...
llvm-svn: 75917
2009-07-16 13:32:49 +00:00
f9fe4036f2
Add sub reg-reg pattern
...
llvm-svn: 75916
2009-07-16 13:32:16 +00:00
a083d7af53
Add xor reg-reg pattern
...
llvm-svn: 75915
2009-07-16 13:31:28 +00:00
65096d6a60
Add or reg-reg pattern.
...
llvm-svn: 75914
2009-07-16 13:30:53 +00:00
18172d786f
Add add reg-reg and reg-imm patterns
...
llvm-svn: 75913
2009-07-16 13:30:15 +00:00
09082fa01a
Add simple reg-reg and reg-imm moves
...
llvm-svn: 75912
2009-07-16 13:29:38 +00:00
cf4ba97dba
Minimal lowering for formal_arguments / ret
...
llvm-svn: 75911
2009-07-16 13:28:59 +00:00
a3ceeaeda5
Add testsuite dir for systemz stuff
...
llvm-svn: 75910
2009-07-16 13:28:22 +00:00
0cceec520c
Combine an unaligned store of unaligned load into a memmove.
...
llvm-svn: 75908
2009-07-16 12:50:48 +00:00
bfdc557c8a
Expand unaligned 32 bit loads from an address which is a constant
...
offset from a 32 bit aligned base as follows:
ldw low, base[offset >> 2]
ldw high, base[(offset >> 2) + 1]
shr low_shifted, low, (offset & 0x3) * 8
shl high_shifted, high, 32 - (offset & 0x3) * 8
or result, low_shifted, high_shifted
Expand 32 bit loads / stores with 16 bit alignment into two 16 bit
loads / stores.
llvm-svn: 75902
2009-07-16 10:42:35 +00:00
25b33cb035
Custom lower unaligned 32 bit stores and loads into libcalls. This is
...
a big code size win since before they were expanding to upto 16
instructions.
llvm-svn: 75901
2009-07-16 10:21:18 +00:00
84517443ca
Let callers decide the sub-register index on the def operand of rematerialized instructions.
...
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
2009-07-16 09:20:10 +00:00
693fbb8fee
implement .include in the lexer/parser instead of passing it into the streamer.
...
llvm-svn: 75896
2009-07-16 06:14:39 +00:00
662da55c5f
Switch invars away from using isTrapping when it really shouldn't be
...
using it.
llvm-svn: 75852
2009-07-15 22:48:29 +00:00
ebe66ab13b
Don't restrict the set of instructions where we try to constant-fold the
...
operands; it's possible to end up with a constant-foldable operand to
most instructions, even those which can't trap.
llvm-svn: 75845
2009-07-15 22:13:34 +00:00
43229fb489
ShortenDeadCopySrcLiveRange needs to be more conservative in multi-kill situations.
...
llvm-svn: 75838
2009-07-15 21:39:50 +00:00
644e74abbe
Fix test so it works on systems where wchar_t != int.
...
llvm-svn: 75827
2009-07-15 20:40:53 +00:00
50267456a4
Test for llvm-gcc patch 75822.
...
llvm-svn: 75824
2009-07-15 20:27:44 +00:00
98ef2852ab
Apparently Darwin doesn't have /dev/full :-(.
...
llvm-svn: 75809
2009-07-15 18:41:11 +00:00
a8edd048c2
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
...
are being properly selected.
llvm-svn: 75797
2009-07-15 17:06:59 +00:00
56ba398889
Add a testcase for raw_ostream error checking.
...
llvm-svn: 75795
2009-07-15 16:47:02 +00:00
57489b0658
Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.
...
llvm-svn: 75788
2009-07-15 15:46:56 +00:00
09ea5709a2
Added llvm-mc support for parsing the .dump and .load directives.
...
llvm-svn: 75786
2009-07-15 15:30:11 +00:00
Evan Cheng