3fefc65c1d
MC: Allow .common as alias for .comm assembler directive. PR10116.
...
llvm-svn: 133349
2011-06-18 13:51:54 +00:00
36c0c6db3f
Improve the heuristic to emit the alias if the number of hard-coded registers
...
are also greater than the alias.
llvm-svn: 133038
2011-06-15 04:31:19 +00:00
e712449688
Heuristic: If the number of operands in the alias are more than the number of
...
operands in the aliasee, don't print the alias.
llvm-svn: 132963
2011-06-14 03:17:20 +00:00
a81247af34
Test that ".byte 1, 2, 3, 4" does the right thing.
...
Requested by nbjoerg!
llvm-svn: 132716
2011-06-07 17:32:17 +00:00
1134ab23df
Basic support for macros with explicit arguments.
...
We still don't handle
* default values
* :req
* :vararg
* \()
llvm-svn: 132656
2011-06-05 02:43:45 +00:00
34fa1684e7
Add support for @GOTPTOFF in i386 mode.
...
llvm-svn: 132643
2011-06-04 17:38:07 +00:00
394f516d16
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
...
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
llvm-svn: 132324
2011-05-31 03:33:27 +00:00
2e84c82750
Use %rbp on a 64 bit test.
...
llvm-svn: 132279
2011-05-29 04:04:50 +00:00
41112a1703
Move ARM specific test into the ARM subdir.
...
llvm-svn: 132255
2011-05-28 11:01:30 +00:00
787dfadc7c
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
...
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
llvm-svn: 132233
2011-05-27 23:46:09 +00:00
041ec4aada
Add the suffix to the Win64 EH data sections' names if given. Add a test for
...
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.
llvm-svn: 132220
2011-05-27 21:38:47 +00:00
ea5dc3a67b
Assorted fixes for Win64 EH unwind info emission:
...
- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.
Add a test for the latter two.
llvm-svn: 132188
2011-05-27 15:10:25 +00:00
43a421e3d5
Add a test for Win64 EH unwind information emission.
...
llvm-svn: 132180
2011-05-27 03:54:43 +00:00
567a1ad7c5
Add a test for the chained directives that I forgot last time.
...
llvm-svn: 132110
2011-05-26 05:17:43 +00:00
006e1c39d0
Test .seh_startchained and .seh_endchained parsing.
...
Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.
The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.
llvm-svn: 132106
2011-05-26 02:45:47 +00:00
2f6ecea19d
Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with
...
them.
I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.
llvm-svn: 132084
2011-05-25 21:43:45 +00:00
828b00c0e1
Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the
...
buggy methods that parse these directives.
llvm-svn: 132045
2011-05-25 04:51:25 +00:00
b0c4f39173
Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another
...
one I found by inspection).
llvm-svn: 132037
2011-05-25 04:08:15 +00:00
fc1e7ce850
Add a test for the .seh_handler directive. Fix problems with the parsing
...
method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.
llvm-svn: 132028
2011-05-25 01:33:42 +00:00
5445213a25
Fix PR9762
...
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
llvm-svn: 132026
2011-05-25 00:35:03 +00:00
f4ce8fde18
Test basic SEH directive-parsing functionality. Fix a latent bug exposed by
...
this test.
llvm-svn: 132004
2011-05-24 21:22:53 +00:00
af5fecb747
add test from PR9164
...
llvm-svn: 131876
2011-05-22 22:35:34 +00:00
819278891a
testcase for PR9378
...
llvm-svn: 131875
2011-05-22 22:32:53 +00:00
a0c9c75df2
Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
...
Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and
modified ARMDisassemblerCore.cpp a little bit.
llvm-svn: 131859
2011-05-22 17:51:04 +00:00
652bfdb1ab
adds some attributes to attribute section when cpu is "xscale"
...
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
2011-05-20 20:10:34 +00:00
1866808384
fixes target address tBL and tBLX and sets relocation type
...
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
llvm-svn: 131748
2011-05-20 20:01:01 +00:00
d0c937d4b2
This fixes one divergence between LLVM and binutils for ARM in the
...
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
llvm-svn: 131674
2011-05-19 20:55:25 +00:00
0fc5e89c82
ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
...
Fixes PR9934.
We really need to start tblgening the relocation info :-(
llvm-svn: 131669
2011-05-19 20:32:34 +00:00
071634612d
Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
...
llvm-svn: 131565
2011-05-18 20:32:41 +00:00
e90c1cb221
sets bit 0 of the function address of thumb function in .symtab
...
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)
Patch by Koan-Sin Tan!
llvm-svn: 131406
2011-05-16 16:17:21 +00:00
b745623b71
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
...
llvm-svn: 131189
2011-05-11 17:00:48 +00:00
99f6735532
On MachO, unlike ELF, there should be no relocation to produce the CIE pointer.
...
llvm-svn: 131149
2011-05-10 20:59:42 +00:00
27390b4a0e
In a debug_frame the cfi offset is to the start of the debug_frame section!
...
llvm-svn: 131129
2011-05-10 15:20:23 +00:00
1ecb12fc57
Add support for producing .deubg_frame sections.
...
llvm-svn: 131121
2011-05-10 03:54:12 +00:00
067ba3c23c
Explicitly request -join-physregs for some tests that depend on it.
...
llvm-svn: 130855
2011-05-04 19:01:59 +00:00
438dc7e1a7
Remove some random comments that snuck in from somewhere.
...
llvm-svn: 130812
2011-05-04 00:48:02 +00:00
d2aa241378
xmm0 is an implicit parameter in this and so shouldn't be in the
...
string template.
Fixes rdar://8493866
llvm-svn: 130747
2011-05-03 01:28:32 +00:00
72032861c6
MCAsmLayout: Add support for computing the symbol offset of variables. Not
...
currently used, because variables don't get reported as being "defined".
llvm-svn: 130524
2011-04-29 18:20:20 +00:00
bea7b93c88
MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection().
...
llvm-svn: 130523
2011-04-29 18:20:17 +00:00
c3c7001844
Add tests for A8.6.110 NOP.
...
llvm-svn: 130345
2011-04-27 23:29:21 +00:00
9b73c8e293
Remove some hard coded CR-LFs. Some of these were the entire files, one of
...
these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.
llvm-svn: 130125
2011-04-25 07:11:23 +00:00
57c892860e
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
...
print out ldr, not ldr.n.
rdar://problem/9267772
llvm-svn: 130008
2011-04-22 19:12:43 +00:00
c3dc486752
Fix relative relocations. This is sufficient for running the rust testsuite with
...
MC :-)
llvm-svn: 129923
2011-04-21 18:36:50 +00:00
ed16477cb9
Behave like gnu as when a relocation crosses sections.
...
llvm-svn: 129850
2011-04-20 14:01:45 +00:00
48592ee5af
Thumb2 BFC was insufficiently encoded.
...
rdar://problem/9292717
llvm-svn: 129619
2011-04-15 22:52:15 +00:00
761e1e3512
A8.6.315 VLD3 (single 3-element structure to all lanes)
...
The a bit must be encoded as 0.
rdar://problem/9292625
llvm-svn: 129618
2011-04-15 22:49:08 +00:00
375249a417
Add encoding tests for flds/filds
...
llvm-svn: 129589
2011-04-15 19:25:31 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
421316178e
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
...
(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
4251b151b1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
...
llvm-svn: 129531
2011-04-14 19:13:28 +00:00
Hans Wennborg