68b0e8456e
Fix off-by-one error.
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(low two bits always zero, so off by one bit of encoded value).
llvm-svn: 134247
2011-07-01 19:07:09 +00:00
703a0fbf39
Hide the call to InitMCInstrInfo into tblgen generated ctor.
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llvm-svn: 134244
2011-07-01 17:57:27 +00:00
4def704a21
Pseudo-ize t2MOVCC[ri].
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t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.
llvm-svn: 134242
2011-07-01 17:14:11 +00:00
c88d6d402a
Eliminate one extra conversion.
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llvm-svn: 134240
2011-07-01 16:59:30 +00:00
bc9e523421
Disable commit 134216 ("Add 134199 back, but disable the optimization when the second
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copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out
because gcc built with dragonegg is going into an infinite loop.
llvm-svn: 134237
2011-07-01 12:01:00 +00:00
92da450ae7
Another misuse of StringRef. MSVC is very sensitive to that kind of error.
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llvm-svn: 134236
2011-07-01 09:23:41 +00:00
f64a39768d
Fix likely typo, reduce number of instruction name collisions.
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llvm-svn: 134235
2011-07-01 06:27:03 +00:00
968af4fee2
Fix use after free.
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llvm-svn: 134234
2011-07-01 04:40:50 +00:00
760e51079a
Avoid DenseMap lookup.
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llvm-svn: 134231
2011-07-01 04:15:02 +00:00
475cd405b0
Fix off by one error. I misunderstood the comment about killedAt.
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llvm-svn: 134229
2011-07-01 03:31:29 +00:00
59066f0da0
Check the liveinterval, not the kill flag.
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llvm-svn: 134228
2011-07-01 02:35:06 +00:00
39af582c57
Don't inflate register classes used by inline asm.
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The constraints are represented by the register class of the original
virtual register created for the inline asm. If the register class were
included in the operand descriptor, we might be able to do this.
For now, just give up on regclass inflation when inline asm is involved.
No test case, this bug hasn't happened yet.
llvm-svn: 134226
2011-07-01 01:24:25 +00:00
f2bcad972d
Improve Mips back-end's handling of DBG_VALUE.
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llvm-svn: 134224
2011-07-01 01:04:43 +00:00
54664ed714
Improve constant folding of undef for cmp and select operators.
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llvm-svn: 134223
2011-07-01 01:03:43 +00:00
29f1db85dd
Add support for the 'j' immediate constraint. This is conditionalized on
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supporting the instruction that the constraint is for 'movw'.
Part of rdar://9119939
llvm-svn: 134222
2011-07-01 01:00:07 +00:00
ca8d9e1341
Improve constant folding of undef for binary operators.
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llvm-svn: 134221
2011-07-01 00:42:17 +00:00
c011d31543
Add support for the ARM 't' register constraint. And another testcase
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for the 'x' register constraint.
Part of rdar://9119939
llvm-svn: 134220
2011-07-01 00:30:46 +00:00
d8e27a584e
Switch SubtargetFeatures from std::string to StringRef.
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llvm-svn: 134219
2011-07-01 00:23:10 +00:00
f09b0f1043
We'll return a null RC by default if we can't match.
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Part of rdar://9119939
llvm-svn: 134217
2011-07-01 00:19:27 +00:00
4b522de5c0
Add 134199 back, but disable the optimization when the second copy is a kill.
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llvm-svn: 134216
2011-07-01 00:16:54 +00:00
f1c74595aa
Add support for the 'x' constraint.
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Part of rdar://9307836 and rdar://9119939
llvm-svn: 134215
2011-07-01 00:14:47 +00:00
c737ac1816
Remove tabs.
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llvm-svn: 134212
2011-06-30 23:59:38 +00:00
1f054f27af
Capitalize the unsigned part of the initializer.
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llvm-svn: 134211
2011-06-30 23:59:16 +00:00
cf2007ca78
Rename Pair to RCPair lacking any better naming ideas.
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llvm-svn: 134210
2011-06-30 23:50:52 +00:00
40cc749788
Improve comment: Show the register the DWARF label is added to.
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llvm-svn: 134209
2011-06-30 23:47:40 +00:00
3f049b8b7e
Use the correct registers on X86_64.
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llvm-svn: 134208
2011-06-30 23:47:14 +00:00
d0e2352b65
Fix a problem with fast-isel return values introduced in r134018.
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We would put the return value from long double functions in the wrong
register.
This fixes gcc.c-torture/execute/conversion.c
llvm-svn: 134205
2011-06-30 23:42:18 +00:00
e9cc901814
Refact ARM Thumb1 tMOVr instruction family.
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Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
llvm-svn: 134204
2011-06-30 23:38:17 +00:00
f45daac30f
Add support for the 'h' constraint.
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Part of rdar://9119939
llvm-svn: 134203
2011-06-30 23:23:01 +00:00
b403f0c4ed
Add target a target hook to get the register number used by the compact unwind
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encoding for the registers it knows about. Return -1 if it can't handle that
register.
llvm-svn: 134202
2011-06-30 23:20:32 +00:00
abe5f97634
Revert my previous patch while I debug llvm-gcc bootstrap.
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llvm-svn: 134201
2011-06-30 22:58:17 +00:00
2fd8d775df
Add one more comment to the FDE verbose asm output.
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llvm-svn: 134200
2011-06-30 22:35:49 +00:00
027cb82657
Don't give up on coalescing A and B when we find
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A = X
B = X
Instead, proceed as if we had found
A = X
B = A
llvm-svn: 134199
2011-06-30 22:24:13 +00:00
c486b47b15
Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>.
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No functional change.
Part of rdar://9119939
llvm-svn: 134198
2011-06-30 22:17:01 +00:00
b98ab91e39
Thumb1 register to register MOV instruction is predicable.
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Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.
llvm-svn: 134197
2011-06-30 22:10:46 +00:00
f166ab447e
Add comments to the FDE.
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llvm-svn: 134196
2011-06-30 22:02:20 +00:00
e7fe47e53b
Add more comments to the ASM output for the CIE's "moves".
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llvm-svn: 134194
2011-06-30 21:45:12 +00:00
2034261972
Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c
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llvm-svn: 134193
2011-06-30 21:30:30 +00:00
567a1aee85
Add comments to the ASM output to help understand the compact unwind and CIE tables.
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llvm-svn: 134191
2011-06-30 21:25:51 +00:00
070f96c567
Create a isFullCopy predicate.
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llvm-svn: 134189
2011-06-30 21:15:52 +00:00
b10a0f223a
Add r134057 back, but splice the predecessor after the successors phi
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nodes.
Original message:
Let simplify cfg simplify bb with only debug and lifetime intrinsics.
llvm-svn: 134182
2011-06-30 20:14:24 +00:00
e4750ef6ec
Pseudo-ize the Thumb tTPsoft instruction.
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It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.
llvm-svn: 134178
2011-06-30 19:38:01 +00:00
efe89ad414
indvars -disable-iv-rewrite: handle cloning binary operators that cannot overflow.
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llvm-svn: 134177
2011-06-30 19:02:17 +00:00
353da73186
Pseudo-ize the t2LDMIA_RET instruction.
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It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.
llvm-svn: 134173
2011-06-30 18:25:42 +00:00
417671a7b1
Pseudo-ize the Thumb tPOP_RET instruction.
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It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.
llvm-svn: 134172
2011-06-30 17:34:04 +00:00
79fd2e7a95
Remove dead code.
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llvm-svn: 134148
2011-06-30 13:17:24 +00:00
23fb54ed15
The enum was moved to ISDOpcodes.h.
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llvm-svn: 134134
2011-06-30 06:37:07 +00:00
cfe3b14d77
Kill dead code.
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llvm-svn: 134131
2011-06-30 02:23:05 +00:00
ed5134a921
Size reducing SP adjusting t2ADDri needs to check predication.
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tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."
llvm-svn: 134130
2011-06-30 02:22:49 +00:00
0b33a323ac
Fix ARMSubtarget feature parsing.
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llvm-svn: 134129
2011-06-30 02:12:44 +00:00
Jim Grosbach