Craig Topper
74650add0e
Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel.
...
llvm-svn: 150363
2012-02-13 05:48:49 +00:00
Craig Topper
6d471c9e49
Recommit r150328. Previous test failures should be fixed by r150360.
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llvm-svn: 150362
2012-02-13 05:10:10 +00:00
Craig Topper
87119fa37f
Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.
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llvm-svn: 150360
2012-02-13 04:30:38 +00:00
NAKAMURA Takumi
0826c17d00
Revert r150328, "Remove more vector_shuffle patterns."
...
It caused 3 failures on pre-penryn and non-x86(generic) hosts.
llvm-svn: 150357
2012-02-13 00:10:15 +00:00
Pete Cooper
71be57bb32
Fixed bug when custom lowering DEC64m on x86.
...
If the DEC node had more than one user, it was doing this lowering but
leaving the original DEC node around and so decrementing twice.
Fixes PR11964.
llvm-svn: 150356
2012-02-13 00:10:03 +00:00
Craig Topper
e24c94af81
Remove more vector_shuffle patterns.
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llvm-svn: 150328
2012-02-12 08:14:35 +00:00
Craig Topper
d40d9eb2b3
Remove more vector_shuffle patterns.
...
llvm-svn: 150321
2012-02-12 01:07:34 +00:00
Craig Topper
330ca97700
Remove more vector_shuffle patterns.
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llvm-svn: 150314
2012-02-11 23:31:01 +00:00
Anton Korobeynikov
c6b4017ce2
Add support for implicit TLS model used with MS VC runtime.
...
Patch by Kai Nacke!
llvm-svn: 150307
2012-02-11 17:26:53 +00:00
Benjamin Kramer
915e3d9568
Don't mix declarations and code.
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llvm-svn: 150305
2012-02-11 16:01:02 +00:00
Benjamin Kramer
428704eb52
Make the EDis tables const.
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llvm-svn: 150304
2012-02-11 14:51:07 +00:00
Benjamin Kramer
478e8de8ef
Reuse the enum names from X86Desc in the X86Disassembler.
...
This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.
llvm-svn: 150303
2012-02-11 14:50:54 +00:00
Craig Topper
981c6cf7b3
Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel.
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llvm-svn: 150299
2012-02-11 07:43:35 +00:00
Craig Topper
11826a6e10
Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel.
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llvm-svn: 150296
2012-02-11 06:24:48 +00:00
Craig Topper
a0cd970b81
More tweaks to get the size of the X86 disassembler tables down.
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llvm-svn: 150167
2012-02-09 08:58:07 +00:00
Craig Topper
487e744f66
Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.
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llvm-svn: 150161
2012-02-09 07:45:30 +00:00
Jakob Stoklund Olesen
4519fd0b21
Handle register masks when searching for EFLAGS clobbers.
...
Calls clobber the flags, but when using register masks there is no
EFLAGS<imp-def> operand.
llvm-svn: 150117
2012-02-09 00:17:22 +00:00
Elena Demikhovsky
1adc1d53dd
Fixed a bug in printing "cmp" pseudo ops.
...
> This IR code
> %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14)
> fails with assertion:
>
> llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed.
> 0 llc 0x0000000001355803
> 1 llc 0x0000000001355dc9
> 2 libpthread.so.0 0x00007f79a30575d0
> 3 libc.so.6 0x00007f79a23a1945 gsignal + 53
> 4 libc.so.6 0x00007f79a23a2f21 abort + 385
> 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240
> 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119
I added the full testing for all possible pseudo-ops of cmp.
I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp.
You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in.
llvm-svn: 150068
2012-02-08 08:37:26 +00:00
Craig Topper
172b9243cd
Remove a couple unneeded intrinsic patterns
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llvm-svn: 150067
2012-02-08 08:29:30 +00:00
Craig Topper
5405571fe0
Remove GCC builtins for vpermilp* intrinsics as clang no longer needs them. Custom lower the intrinsics to the vpermilp target specific node and remove intrinsic patterns.
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llvm-svn: 150060
2012-02-08 06:36:57 +00:00
Evan Cheng
1b81fddd65
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
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llvm-svn: 150008
2012-02-07 22:50:41 +00:00
Craig Topper
b27fd77c3f
Add instruction selection for 256-bit VPSHUFD and 128-bit VPERMILPS/VPERMILPD.
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llvm-svn: 149968
2012-02-07 06:28:42 +00:00
Derek Schuff
8b2dcad4b5
Enable streaming of bitcode
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This CL delays reading of function bodies from initial parse until
materialization, allowing overlap of compilation with bitcode download.
llvm-svn: 149918
2012-02-06 22:30:29 +00:00
Chris Lattner
8213c8af29
Remove some dead code and tidy things up now that vectors use ConstantDataVector
...
instead of always using ConstantVector.
llvm-svn: 149912
2012-02-06 21:56:39 +00:00
Benjamin Kramer
2496717052
X86: Don't call malloc for 4 bits. No functionality change.
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llvm-svn: 149866
2012-02-06 12:06:18 +00:00
Craig Topper
1f71057747
Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd decoding.
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llvm-svn: 149859
2012-02-06 07:17:51 +00:00
Duncan Sands
ae22c60f90
Persuade GCC that there is nothing worth warning about here (there isn't).
...
llvm-svn: 149834
2012-02-05 14:20:11 +00:00
Chandler Carruth
ebd90c58e6
Begin fleshing out more convenience predicates in llvm::Triple and
...
convert at least one client over to use them. Subsequent patches both to
LLVM and Clang will try to convert more people over to a common set of
predicates.
This round of predicates is focused on OS-categorization predicates.
llvm-svn: 149815
2012-02-05 08:26:40 +00:00
Craig Topper
c4965bce14
Convert assert(0) to llvm_unreachable
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llvm-svn: 149814
2012-02-05 07:21:30 +00:00
Craig Topper
4ed7278ff4
Convert assert(0) to llvm_unreachable in X86 Target directory.
...
llvm-svn: 149809
2012-02-05 05:38:58 +00:00
Craig Topper
83f3bdaa45
Convert some assert(0) in default of switch statements to llvm_unreachable.
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llvm-svn: 149808
2012-02-05 03:43:23 +00:00
Craig Topper
1d471e31ba
Add target specific node for PMULUDQ. Change patterns to use it and custom lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies.
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llvm-svn: 149807
2012-02-05 03:14:49 +00:00
Craig Topper
4daa67483d
Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file.
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llvm-svn: 149795
2012-02-05 00:55:56 +00:00
Andrew Trick
f8ea108c05
TargetPassConfig: confine the MC configuration to TargetMachine.
...
Passes prior to instructon selection are now split into separate configurable stages.
Header dependencies are simplified.
The bulk of this diff is simply removal of the silly DisableVerify flags.
Sorry for the target header churn. Attempting to stabilize them.
llvm-svn: 149754
2012-02-04 02:56:59 +00:00
Craig Topper
47e6d26911
Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate performs the same calculation.
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llvm-svn: 149683
2012-02-03 06:52:33 +00:00
Craig Topper
d5ffe0900d
Remove unnecessary qualification on 256-bit vector handling in LowerBUILD_VECTOR. Condition was already guaranteed by earlier code.
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llvm-svn: 149680
2012-02-03 06:32:21 +00:00
Andrew Trick
ccb673659a
Added TargetPassConfig. The first little step toward configuring codegen passes.
...
Allows command line overrides to be centralized in LLVMTargetMachine.cpp.
LLVMTargetMachine can intercept common passes and give precedence to command line overrides.
Allows adding "internal" target configuration options without touching TargetOptions.
Encapsulates the PassManager.
Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs.
Allows modifying the target configuration hooks without rebuilding the world.
llvm-svn: 149672
2012-02-03 05:12:41 +00:00
Andrew Trick
808a7a6ce6
whitespace
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llvm-svn: 149671
2012-02-03 05:12:30 +00:00
Lang Hames
bb682450f9
Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.
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llvm-svn: 149655
2012-02-03 01:13:49 +00:00
Jakob Stoklund Olesen
5e1ac45b93
Require non-NULL register masks.
...
It doesn't seem worthwhile to give meaning to a NULL register mask
pointer. It complicates all the code using register mask operands.
llvm-svn: 149646
2012-02-02 23:52:57 +00:00
Elena Demikhovsky
6fbb4d2842
Minor change in signature of the getZeroVector()
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llvm-svn: 149601
2012-02-02 09:20:18 +00:00
Elena Demikhovsky
fb44980b41
Optimization for SIGN_EXTEND operation on AVX.
...
Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32
extensions.
llvm-svn: 149600
2012-02-02 09:10:43 +00:00
Francois Pichet
26f302d568
Unbreak the MSVC build.
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llvm-svn: 149599
2012-02-02 08:36:09 +00:00
Lang Hames
0269caafa6
Set EFLAGS correctly in EmitLoweredSelect on X86.
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llvm-svn: 149597
2012-02-02 07:48:37 +00:00
Andrew Trick
8523b16ff5
Instruction scheduling itinerary for Intel Atom.
...
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
Mon P Wang
9f05206659
Avoid creating an extract element to an illegal type after LegalizeTypes has run.
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llvm-svn: 149548
2012-02-01 22:15:20 +00:00
Chad Rosier
e273cb08c4
Tidy up.
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llvm-svn: 149521
2012-02-01 18:45:51 +00:00
Elena Demikhovsky
824eed70a6
Passing AVX 256-bit structures in Win64 was wrong.
...
Fixed Win64 calling conventions.
llvm-svn: 149494
2012-02-01 10:46:14 +00:00
Elena Demikhovsky
34cca175ab
Shortened code in shuffle masks
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llvm-svn: 149493
2012-02-01 10:33:05 +00:00
Elena Demikhovsky
0e48c70ba7
Optimization for "truncate" operation on AVX.
...
Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles.
llvm-svn: 149485
2012-02-01 07:56:44 +00:00
Craig Topper
9cdb8bdf04
Don't create VBROADCAST nodes if any nodes use the chain result from the load. Fixes PR11900.
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llvm-svn: 149478
2012-02-01 06:51:58 +00:00
Devang Patel
a173ee56fd
Add assembler dialect attribute in asm parser which lets target specific asm parser change dialect on the fly.
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llvm-svn: 149396
2012-01-31 18:14:05 +00:00
Craig Topper
b85e40f738
Remove pcmpgt/pcmpeq intrinsics as clang is not using them.
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llvm-svn: 149367
2012-01-31 06:52:44 +00:00
Evan Cheng
4e7992eeba
PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.
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llvm-svn: 149294
2012-01-30 23:10:32 +00:00
Devang Patel
7cdb2ff6b5
Intel syntax. Adjust special code, used to recognize cmp<comparison code>{ss,sd,ps,pd}, for intel syntax.
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llvm-svn: 149291
2012-01-30 22:47:12 +00:00
Devang Patel
9a9bb5c5db
Intel syntax. Support .intel_syntax directive.
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llvm-svn: 149270
2012-01-30 20:02:42 +00:00
Benjamin Kramer
396c590818
Fix refacto.
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llvm-svn: 149269
2012-01-30 20:01:35 +00:00
Douglas Gregor
e577cfe172
Eliminate narrowing conversion in initializer list, to make C++11 happy
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llvm-svn: 149254
2012-01-30 16:57:18 +00:00
Benjamin Kramer
20af25f47b
X86: Simplify shuffle mask generation code.
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llvm-svn: 149248
2012-01-30 15:16:21 +00:00
Craig Topper
516cba3380
Fix pattern for memory form of PSHUFD for use with FP vectors to remove bitcast to an integer vector that normal code wouldn't have. Also remove bitcasts from code that turns splat vector loads into a shuffle as it was making the broken pattern necessary.
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llvm-svn: 149232
2012-01-30 07:50:31 +00:00
Craig Topper
ca29bcfc10
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
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llvm-svn: 149216
2012-01-30 01:10:15 +00:00
Devang Patel
63fe5697f4
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
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llvm-svn: 149142
2012-01-27 19:48:28 +00:00
Craig Topper
5639e9e8fb
Move some patterns back near their instructions and use AddedComplexity to fix priority. Merge some patterns into their instruction definition.
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llvm-svn: 149122
2012-01-27 07:09:40 +00:00
Jim Grosbach
8f28dbdde5
Keep source location information for X86 MCFixup's.
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llvm-svn: 149106
2012-01-27 00:51:27 +00:00
Jakob Stoklund Olesen
fc9dce25f7
Handle call-clobbered ymm registers on Win64.
...
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
llvm-svn: 149088
2012-01-26 22:59:28 +00:00
Victor Umansky
5f29b0e57b
Fix for the following bug in AVX codegen for double-to-int conversions:
...
. "fptosi" and "fptoui" IR instructions are defined with round-to-zero rounding mode.
. Currently for AVX mode for <4xdouble> and <8xdouble> the "VCVTPD2DQ.128" and "VCVTPD2DQ.256" instructions are selected (for .fp_to_sint. DAG node operation ) by AVX codegen. However they use round-to-nearest-even rounding mode.
. Consequently, the conversion produces incorrect numbers.
The fix is to replace selection of VCVTPD2DQ instructions with VCVTTPD2DQ instructions. The latter use truncate (i.e. round-to-zero) rounding mode.
As .fp_to_sint. DAG node operation is used only for lowering of "fptosi" and "fptoui" IR instructions, the fix in X86InstrSSE.td definition file doesn.t have an impact on other LLVM flows.
The patch includes changes in the .td file, LIT test for the changes and a fix in a legacy LIT test (which produced asm code conflicting with LLVN IR spec).
llvm-svn: 149056
2012-01-26 08:51:39 +00:00
Craig Topper
86e44bc829
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
...
llvm-svn: 149054
2012-01-26 07:51:55 +00:00
Craig Topper
1c0e22f57a
Fix AVX vs SSE patterns ordering issue for VPCMPESTRM and VPCMPISTRM.
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llvm-svn: 149053
2012-01-26 07:31:30 +00:00
Craig Topper
b91760eff8
Remove some more patterns by custom lowering intrinsics to target specific nodes.
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llvm-svn: 149052
2012-01-26 07:18:03 +00:00
Chris Lattner
33633a90a0
fix a bug I introduced in r148929, this is not a splat!
...
Thanks to Eli for noticing.
llvm-svn: 148947
2012-01-25 09:56:22 +00:00
Craig Topper
7834900950
Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns.
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llvm-svn: 148933
2012-01-25 06:43:11 +00:00
Chris Lattner
47a86bdbe2
use ConstantVector::getSplat in a few places.
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llvm-svn: 148929
2012-01-25 06:02:56 +00:00
Craig Topper
ce4f9c5668
Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary.
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llvm-svn: 148927
2012-01-25 05:37:32 +00:00
Craig Topper
5bcf070e68
Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago.
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llvm-svn: 148922
2012-01-25 04:42:03 +00:00
Craig Topper
3ad5bc019a
Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions.
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llvm-svn: 148914
2012-01-25 03:52:09 +00:00
Devang Patel
a410ed3ced
Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax.
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llvm-svn: 148864
2012-01-24 21:43:36 +00:00
Elena Demikhovsky
0b0c5d8c4c
ZERO_EXTEND operation is optimized for AVX.
...
v8i16 -> v8i32, v4i32 -> v4i64 - used vpunpck* instructions.
llvm-svn: 148803
2012-01-24 13:54:13 +00:00
Craig Topper
0d8e67aebd
Add comments near load pattern fragments indicating that all integer vector loads are promoted to v2i64 or v4i64 so that no one tries to reintroduce pattern fragments for other types.
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llvm-svn: 148771
2012-01-24 03:03:17 +00:00
Devang Patel
eba7d3dba9
Fix typo.
...
llvm-svn: 148751
2012-01-23 23:56:33 +00:00
Devang Patel
cf893a437e
Intel syntax: Robustify parsing of memory operand's displacement experssion.
...
llvm-svn: 148737
2012-01-23 22:35:25 +00:00
Devang Patel
e660fdd953
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
...
llvm-svn: 148721
2012-01-23 20:20:06 +00:00
Devang Patel
880bc1644b
Intel syntax: Parse segment registers.
...
llvm-svn: 148712
2012-01-23 18:31:58 +00:00
Craig Topper
edd1d0acfc
Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the intrinsic patterns.
...
llvm-svn: 148687
2012-01-23 08:18:28 +00:00
Craig Topper
6b90c5d03e
Update more places to use target specific nodes for vector shifts instead of intrinsics.
...
llvm-svn: 148685
2012-01-23 06:46:22 +00:00
Craig Topper
5e80db4e4f
Custom lower vector shift intrinsics to target specific nodes and remove the patterns that are no longer needed.
...
llvm-svn: 148684
2012-01-23 06:16:53 +00:00
Craig Topper
20c98df340
Remove pattern fragments for v32i8, v16i16, v8i32, v16i8, v8i16, and v4i32 loads. All integer vector loads are promoted to v2i64 or v4i64 so these pattern fragments can never match. Fix or remove patterns that used these fragments.
...
llvm-svn: 148672
2012-01-23 00:06:44 +00:00
Craig Topper
0b7ad76bd0
Combine X86 CMPPD and CMPPS node types. Simplifies selection code and pattern matching.
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llvm-svn: 148670
2012-01-22 23:36:02 +00:00
Craig Topper
bd4884371b
Merge PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ and PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ X86 ISD node types into only two node types. Simplifying opcode selection and pattern matching.
...
llvm-svn: 148667
2012-01-22 22:42:16 +00:00
Craig Topper
094626414d
Add target specific ISD node types for SSE/AVX vector shuffle instructions and change all the code that used to create intrinsic nodes to create the new nodes instead.
...
llvm-svn: 148664
2012-01-22 19:15:14 +00:00
Craig Topper
a4ed5246d8
Make code a little less verbose.
...
llvm-svn: 148651
2012-01-22 03:07:48 +00:00
Craig Topper
cb3433cd58
Remove unused X86 ISD node type defines.
...
llvm-svn: 148644
2012-01-22 01:15:56 +00:00
Craig Topper
123adfa0f3
Move some vector shift patterns into their instruction definitions.
...
llvm-svn: 148643
2012-01-22 00:41:20 +00:00
Craig Topper
dcaa5fbd08
Add memory patterns for some of the fp<->integer conversion instructions. Fold some patterns into instruction definitions.
...
llvm-svn: 148641
2012-01-21 18:37:15 +00:00
Benjamin Kramer
5cff13a3fb
Remove unused variables.
...
llvm-svn: 148635
2012-01-21 10:42:44 +00:00
Craig Topper
39bc1e4d25
Fix PR11819 introduced by r148537. I'd commit the test case, but the generated code is terrible as it gets fully scalarized. Expect a future commit to fix that.
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llvm-svn: 148632
2012-01-21 08:49:33 +00:00
Devang Patel
ce6a2ca8c8
Intel syntax: Robustify register parsing.
...
llvm-svn: 148591
2012-01-20 22:32:05 +00:00
David Blaikie
46a9f016c5
More dead code removal (using -Wunreachable-code)
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llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Devang Patel
d0930fff85
Intel syntax: Parse ... PTR [-8]
...
llvm-svn: 148570
2012-01-20 21:21:01 +00:00
Devang Patel
f36613cb45
Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.
...
llvm-svn: 148569
2012-01-20 21:14:06 +00:00
Craig Topper
a409479023
Improve 256-bit shuffle splitting to allow 2 sources in each 128-bit lane. As long as only a single lane of the source is used in the lane in the destination. This makes the splitting match much closer to what happens with 256-bit shuffles when AVX is disabled and only 128-bit XMM is allowed.
...
llvm-svn: 148537
2012-01-20 09:29:03 +00:00
Craig Topper
3469212c82
Add support for selecting 256-bit PALIGNR.
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llvm-svn: 148532
2012-01-20 05:53:00 +00:00
Eli Friedman
32c7c25dcb
Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.
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llvm-svn: 148513
2012-01-20 00:05:46 +00:00
Devang Patel
f83dcfd052
Post process 'and', 'sub' instructions and select better encoding, if available.
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llvm-svn: 148489
2012-01-19 18:40:55 +00:00
Devang Patel
2529dd9e00
Intel syntax: There is no need to create unary expr for simple negative displacement.
...
llvm-svn: 148486
2012-01-19 18:15:51 +00:00
Devang Patel
4a62ff9bcb
Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
...
llvm-svn: 148485
2012-01-19 17:53:25 +00:00
Craig Topper
a875b7ccc7
Folding table additions and fixes for AVX.
...
llvm-svn: 148467
2012-01-19 08:50:38 +00:00
Craig Topper
80576e8d1f
Merge 128-bit and 256-bit SHUFPS/SHUFPD handling.
...
llvm-svn: 148466
2012-01-19 08:19:12 +00:00
Nick Lewycky
ecc0084f72
Add a TargetOption for disabling tail calls.
...
llvm-svn: 148442
2012-01-19 00:34:10 +00:00
Jakob Stoklund Olesen
ff482f733b
Add experimental -x86-use-regmask command line option.
...
It adds register mask operands to x86 call instructions. Once all the
backend passes support register mask operands, this will be permanently
enabled.
llvm-svn: 148438
2012-01-18 23:52:22 +00:00
Jakob Stoklund Olesen
f1fb1d2375
Ignore register mask operands when lowering instructions to MC.
...
This is similar to implicit register operands. MC doesn't understand
register liveness and call clobbers.
llvm-svn: 148437
2012-01-18 23:52:19 +00:00
Devang Patel
de47cced25
Process instructions after match to select alternative encoding which may be more desirable.
...
llvm-svn: 148431
2012-01-18 22:42:29 +00:00
Jim Grosbach
aba3de99c0
Tidy up. MCAsmBackend naming conventions.
...
llvm-svn: 148400
2012-01-18 18:52:16 +00:00
Jakob Stoklund Olesen
f43b599550
Add a CoveredBySubRegs property to Register descriptions.
...
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
llvm-svn: 148363
2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
d51a710bde
Move X86 callee saved register lists to the X86CallConv .td file.
...
Add a trivial implementation of the getCallPreservedMask() hook.
llvm-svn: 148347
2012-01-17 22:47:01 +00:00
Devang Patel
c9ed518792
Intel syntax: Fix parser match class to check memory operand size.
...
llvm-svn: 148338
2012-01-17 21:48:03 +00:00
Devang Patel
a7143b6a2b
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
...
llvm-svn: 148334
2012-01-17 21:25:10 +00:00
Devang Patel
2ed6718616
Untabify.
...
llvm-svn: 148322
2012-01-17 19:09:22 +00:00
Devang Patel
8b39be79ad
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
...
llvm-svn: 148321
2012-01-17 19:08:07 +00:00
Devang Patel
41b9ddeb7a
Intel syntax: Robustify memory operand parsing.
...
llvm-svn: 148312
2012-01-17 18:00:18 +00:00
Nadav Rotem
86c3807b99
Fix warning.
...
llvm-svn: 148301
2012-01-17 09:31:09 +00:00
Nadav Rotem
86e5390dbf
Fix 11769.
...
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.
llvm-svn: 148298
2012-01-17 09:13:19 +00:00
Craig Topper
9cafcd8baa
Remove unnecessary AVX check from an assert. hasSSE2 is enough.
...
llvm-svn: 148295
2012-01-17 08:23:44 +00:00
Craig Topper
37b10ef250
Fix a crasher when PerformShiftCombine receives a BUILD_VECTOR of all UNDEF. Probably could use better handling in DAG combine or getNode. Fixes PR11772.
...
llvm-svn: 148285
2012-01-17 04:44:50 +00:00
Eli Friedman
206ca569aa
Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.
...
llvm-svn: 148240
2012-01-16 16:42:21 +00:00
Eli Friedman
75e3db4c7a
Get rid of unused codegen-only instruction.
...
llvm-svn: 148239
2012-01-16 16:29:35 +00:00
Craig Topper
db8890aedd
Give priority to AVX over SSE for 128-bit floating point unpck instructions.
...
llvm-svn: 148233
2012-01-16 09:56:42 +00:00
Nadav Rotem
57935243bd
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.
...
We know that the blend instructions only use the MSB, so if the mask is
sign-extended then we can convert it into a SHL instruction. This is a
common pattern because the type-legalizer sign-extends the i1 type which
is used by the LLVM-IR for the condition.
Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL.
llvm-svn: 148225
2012-01-15 19:27:55 +00:00
Benjamin Kramer
339ced4e34
Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through CodeGen.
...
llvm-svn: 148218
2012-01-15 13:16:05 +00:00
Craig Topper
c10e1abaf3
Fix the memop type on a couple 256-bit AVX instructions that were using f128mem instead of f256mem.
...
llvm-svn: 148196
2012-01-14 18:29:57 +00:00
Craig Topper
d78429f850
Add a bunch of AVX instructions to the folding tables. Also fixed the alignment on 256-bit AVX2 instructions.
...
llvm-svn: 148194
2012-01-14 18:14:53 +00:00
Chad Rosier
71a185c5c6
Fix pasto from r146196.
...
llvm-svn: 148167
2012-01-14 01:50:21 +00:00
Devang Patel
7066d28043
Revert r148131, it was committed before it was ready.
...
llvm-svn: 148134
2012-01-13 19:28:58 +00:00
Devang Patel
7ecdc6d4f5
Refactor.
...
llvm-svn: 148131
2012-01-13 19:12:18 +00:00
Craig Topper
e52d86a740
Convert SHUFPD with the same register for both sources to PSHUFD if it would prevent a register copy. Similar to SHUFPS, but requires the mask to be converted.
...
llvm-svn: 148112
2012-01-13 09:21:41 +00:00
Craig Topper
b1c2ebf6ee
use v8i32 as optimal mem type over v8f32 if AVX2 is enabled. Similar to SSE2 vs SSE1.
...
llvm-svn: 148109
2012-01-13 08:32:21 +00:00
Craig Topper
cb7e13d7c0
Make X86 instruction selection use 256-bit VPXOR for build_vector of all ones if AVX2 is enabled. This gives the ExeDepsFix pass a chance to choose FP vs int as appropriate. Also use v8i32 as the type for getZeroVector if AVX2 is enabled. This is consistent with SSE2 using prefering v4i32.
...
llvm-svn: 148108
2012-01-13 08:12:35 +00:00
Craig Topper
9f14d9f939
Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match v4i64 and v8i32.
...
llvm-svn: 148106
2012-01-13 06:59:47 +00:00
Craig Topper
a4c5a47b97
Use 8i32 constant pool entry for converting AVX2_SETALLONES. Possibly fixes PR11750.
...
llvm-svn: 148101
2012-01-13 06:12:41 +00:00
Craig Topper
2aa07f832e
Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
...
llvm-svn: 148096
2012-01-13 05:04:25 +00:00
Bill Wendling
9c8456f7ef
Fix off-by-one error.
...
llvm-svn: 148077
2012-01-13 00:41:53 +00:00
Bill Wendling
ee5eaebc58
Fix the code that was WRONG.
...
The registers are placed into the saved registers list in the reverse order,
which is why the original loop was written to loop backwards.
llvm-svn: 148064
2012-01-12 23:05:03 +00:00
Elena Demikhovsky
060f6ccdb8
Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure
...
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed.
Added a test.
llvm-svn: 148044
2012-01-12 20:33:10 +00:00
Rafael Espindola
00e861ed57
Support segmented stacks on 64-bit FreeBSD.
...
This patch uses tcb_spare field in the tcb structure to store info.
Patch by Jyun-Yan You.
llvm-svn: 148041
2012-01-12 20:24:30 +00:00
Rafael Espindola
10745d3381
Support segmented stacks on win32.
...
Uses the pvArbitrary slot of the TIB, which is reserved for applications. We
only support frames with a static size.
llvm-svn: 148040
2012-01-12 20:22:08 +00:00
Devang Patel
4a6e778aae
Rename X86ATTAsmParser -> X86AsmParser
...
We are using one parser to parse att as well as intel style syntax.
llvm-svn: 148032
2012-01-12 18:03:40 +00:00
Benjamin Kramer
9ece950ddb
After Jakob's r147938 exception handling on i386 was completely broken.
...
Restore the (obviously wrong) behavior from before r147938 without relying on
undefined behavior. Add a fat FIXME note.
This should fix nightly tester failures.
llvm-svn: 148030
2012-01-12 17:37:18 +00:00
Nadav Rotem
0a0a829bea
Fix a bug in the AVX 256-bit shuffle code in cases where the splat element is on the boundary of two 128-bit vectors.
...
The attached testcase was stuck in an endless loop.
llvm-svn: 148027
2012-01-12 15:31:55 +00:00
Benjamin Kramer
5b3aa60b44
X86: Generalize the x << (y & const) optimization to also catch masks with more set bits set than 31 or 63.
...
llvm-svn: 148024
2012-01-12 12:41:34 +00:00
Devang Patel
fc6be102ae
Add predicate method check match memory operand size, if available.
...
In att style asm syntax memory operand size is derived from suffix attached with mnemonic. In intel style asm syntax it is part of memory operand hence predicate method check is required to select appropriate instruction.
llvm-svn: 148006
2012-01-12 01:51:42 +00:00
Devang Patel
46831de240
Add intel style operand parser skeleton.
...
This is a work in progress.
llvm-svn: 148002
2012-01-12 01:36:43 +00:00
Chandler Carruth
eb21da060b
Switch all of the uses of my InsertDAGNode helper to follow the exact
...
same pattern. We already had this pattern is a few places, but others
tried to make a rough approximation of an actual DAG structure. As not
everywhere went to this trouble, nothing could rely on this being done.
In fact, I've checked all references to these node Ids, and the ones
that are using the topo-sort properties are actually satisfied with
a strict-weak-ordering. The requirement appears to be that Use >= Def.
I've added a big blurb of comments to this bit of the transform to
clarify why the order is so important for the next reader of the code.
I'm starting with this change as it is very small, and trivially
reverted if something breaks or the >= above really does need to be >.
If that proves the case, we can hide the problem by reverting this
patch, but the problem exists elsewhere as well, and so a more
comprehensive solution will be needed.
llvm-svn: 148001
2012-01-12 01:34:44 +00:00
Rafael Espindola
d90466bcbf
Support segmented stacks on mac.
...
This uses TLS slot 90, which actually belongs to JavaScriptCore. We only support
frames with static size
Patch by Brian Anderson.
llvm-svn: 147960
2012-01-11 19:00:37 +00:00
Rafael Espindola
4eecacb9c8
Generate the segmented stack prologue for fastcc too.
...
Patch by Brian Anderson.
llvm-svn: 147958
2012-01-11 18:41:19 +00:00
Chandler Carruth
3212a34269
Revert r147945 which disabled an addressing mode transformation. I had
...
hoped this would revive one of the llvm-gcc selfhost build bots, but it
didn't so it doesn't appear that my transform is the culprit.
If anyone else is seeing failures, please let me know!
llvm-svn: 147957
2012-01-11 18:36:12 +00:00
Rafael Espindola
2b89448d60
Use unsigned comparison in segmented stack prologue.
...
This is a comparison of two addresses, and GCC does the comparison unsigned.
Patch by Brian Anderson.
llvm-svn: 147954
2012-01-11 18:23:35 +00:00
Rafael Espindola
6635ae1c17
Explicitly set the scale to 1 on some segstack prologue instrs.
...
Patch by Brian Anderson.
llvm-svn: 147952
2012-01-11 18:14:03 +00:00
Jan Sjödin
21f83d9f36
Add XOP Intrinsics and tests
...
llvm-svn: 147949
2012-01-11 15:20:20 +00:00
Nadav Rotem
baae7e4577
Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not zero untouched elements. Use INSERT_VECTOR_ELT instead.
...
llvm-svn: 147948
2012-01-11 14:07:51 +00:00
Chandler Carruth
9bc48e5215
Disable the transformation I added in r147936 to see if it fixes some
...
strange build bot failures that look like a miscompile into an infloop.
I'll investigate this tomorrow, but I'd both like to know whether my
patch is the culprit, and get the bots back to green.
llvm-svn: 147945
2012-01-11 12:17:47 +00:00
Chandler Carruth
3eacfb83fa
Hoist a really redundant code pattern into a helper function, and delete
...
lots of lines of code. No functionality changed.
llvm-svn: 147942
2012-01-11 11:04:36 +00:00
Chandler Carruth
b0049f4a43
Simplify the AND-rooted mask+shift checking code to match that of the
...
SRL-rooted code.
llvm-svn: 147941
2012-01-11 09:35:04 +00:00
Chandler Carruth
3dbcda8478
Unify the interface of the three mask+shift transform helpers, and
...
factor the differences that were hiding in one of them into its other
caller, the SRL handling code. No change in behavior.
llvm-svn: 147940
2012-01-11 09:35:02 +00:00
Chandler Carruth
aa01e6661a
Clarify and make explicit some of the requirements for transforming
...
mask+shift pairs at the beginning of the ISD::AND case block, and then
hoist the final pattern into a helper function, simplifying and
reflowing it appropriately. This should have no observable behavior
change, but several simplifications fell out of this such as directly
computing the new mask constant, etc.
llvm-svn: 147939
2012-01-11 09:35:00 +00:00
Jakob Stoklund Olesen
6039983755
Fix undefined code and reenable test case.
...
I don't think the compact encoding code is right, but at least is has
defined behavior now.
llvm-svn: 147938
2012-01-11 09:08:04 +00:00
Chandler Carruth
51d3076bbf
Hoist the logic to transform shift+mask combinations into sub-register
...
extracts and scaled addressing modes into its own helper function. No
functionality changed here, just hoisting and layout fixes falling out
of that hoisting.
llvm-svn: 147937
2012-01-11 08:48:20 +00:00
Chandler Carruth
55b2cdee26
Teach the X86 instruction selection to do some heroic transforms to
...
detect a pattern which can be implemented with a small 'shl' embedded in
the addressing mode scale. This happens in real code as follows:
unsigned x = my_accelerator_table[input >> 11];
Here we have some lookup table that we look into using the high bits of
'input'. Each entity in the table is 4-bytes, which means this
implicitly gets turned into (once lowered out of a GEP):
*(unsigned*)((char*)my_accelerator_table + ((input >> 11) << 2));
The shift right followed by a shift left is canonicalized to a smaller
shift right and masking off the low bits. That hides the shift right
which x86 has an addressing mode designed to support. We now detect
masks of this form, and produce the longer shift right followed by the
proper addressing mode. In addition to saving a (rather large)
instruction, this also reduces stalls in Intel chips on benchmarks I've
measured.
In order for all of this to work, one part of the DAG needs to be
canonicalized *still further* than it currently is. This involves
removing pointless 'trunc' nodes between a zextload and a zext. Without
that, we end up generating spurious masks and hiding the pattern.
llvm-svn: 147936
2012-01-11 08:41:08 +00:00
Lang Hames
995c63329a
Fixed order of operands in comment to match code.
...
llvm-svn: 147890
2012-01-10 22:53:20 +00:00
Joerg Sonnenberger
96cd35cf6d
Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.
...
Add a test that checks the stack alignment of a simple function for
Darwin, Linux and NetBSD for 32bit and 64bit mode.
llvm-svn: 147888
2012-01-10 22:43:53 +00:00
Chad Rosier
1a8f0ccd8c
Add missing VEX predicates to VMOVSDto64rr/VMOVSDto64mr. This fixes a few
...
failing test cases on our internal AVX nightly tester.
rdar://10663637
llvm-svn: 147881
2012-01-10 22:14:06 +00:00
Bill Wendling
d5ab02600e
For i386, don't use the generic code.
...
As the comment around 7746 says, it's better to use the x87 extended precision
here than SSE. And the generic code doesn't know how to do that. It also regains
the speed lost for the uint64_to_float.c testcase.
<rdar://problem/10669858>
llvm-svn: 147869
2012-01-10 19:41:30 +00:00
Devang Patel
67bf992a8f
Add definition for intel asm variant.
...
Right now, this just adds additional entries in match table. The parser does not use them yet.
llvm-svn: 147859
2012-01-10 17:51:54 +00:00
David Blaikie
edbb58c577
Remove unnecessary default cases in switches that cover all enum values.
...
llvm-svn: 147855
2012-01-10 16:47:17 +00:00
Benjamin Kramer
077ae1d760
Add definitions for AMD's bobcat (aka btver1)
...
llvm-svn: 147846
2012-01-10 11:50:02 +00:00
Craig Topper
430f3f1bd6
Fix a crash in AVX2 when trying to broadcast a double into a 128-bit vector. There is no vbroadcastsd xmm, but we do need to support 64-bit integers broadcasted into xmm. Also factor the AVX check into the isVectorBroadcast function. This makes more sense since the AVX2 check was already inside.
...
llvm-svn: 147844
2012-01-10 08:23:59 +00:00
Craig Topper
b0c0f72ae6
Remove hasXMM/hasXMMInt functions. Move callers to hasSSE1/hasSSE2. This is the final piece to remove the AVX hack that disabled SSE.
...
llvm-svn: 147843
2012-01-10 06:54:16 +00:00
Craig Topper
d97bbd7b60
Remove hasSSE*orAVX functions and change all callers to use just hasSSE*. AVX is now an SSE level and no longer disables SSE checks.
...
llvm-svn: 147842
2012-01-10 06:37:29 +00:00
Craig Topper
eb8f9e9e5b
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget.
...
llvm-svn: 147841
2012-01-10 06:30:56 +00:00
Devang Patel
29ba4f97e6
Fix asm string wrt variants.
...
llvm-svn: 147805
2012-01-09 21:32:02 +00:00
Devang Patel
85d684a4d9
Split AsmParser into two components - AsmParser and AsmParserVariant
...
AsmParser holds info specific to target parser.
AsmParserVariant holds info specific to asm variants supported by the target.
llvm-svn: 147787
2012-01-09 19:13:28 +00:00
Chandler Carruth
c16622daff
Don't rely on the fact that shift values are never very large, and thus
...
this substraction will result in small negative numbers at worst which
become very large positive numbers on assignment and are thus caught by
the <=4 check on the next line. The >0 check clearly intended to catch
these as negative numbers.
Spotted by inspection, and impossible to trigger given the shift widths
that can be used.
llvm-svn: 147773
2012-01-09 09:47:25 +00:00
Craig Topper
f287a4509e
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.
...
llvm-svn: 147770
2012-01-09 09:02:13 +00:00
Craig Topper
b89805c77d
Add HasAVX predicate to some of the AVX patterns.
...
llvm-svn: 147769
2012-01-09 08:34:00 +00:00
Craig Topper
a51f7f75c2
Reorder a bunch of patterns to put the AVX version first thus giving it priority over the SSE version. Another step towards trying to remove the AVX hack that disables SSE from X86Subtarget.
...
llvm-svn: 147768
2012-01-09 08:10:38 +00:00
Craig Topper
ef7f5bf8c9
Clean up patterns for MOVNT*. Not sure why there were floating point types on MOVNTPS and MOVNTDQ. And v4i64 was completely missing.
...
llvm-svn: 147767
2012-01-09 06:52:46 +00:00
Craig Topper
c1f5622ad3
Mark MOVNTI as being supported in SSE2 OR AVX mode. This instruction has no AVX equivalent so we should use the SSE version.
...
llvm-svn: 147766
2012-01-09 06:38:55 +00:00
Craig Topper
a081644f8a
Move SSE2 logical operations PAND/POR/PXOR/PANDN above SSE1 logical operations ANDPS/ORPS/XORPS/ANDNPS. This fixes a pattern ordering issue that meant that the SSE2 instructions could never be directly selected since the SSE1 patterns would always match first. This is largely moot with the ExeDepsFix pass, but I'm trying to audit for all such ordering issues.
...
llvm-svn: 147765
2012-01-09 05:07:01 +00:00
Craig Topper
210e4f81b3
Change some places that were checking for AVX OR SSE1/2 to use hasXMM/hasXMMInt instead. Also fix one place that checked SSE3, but accidentally excluded AVX to use hasSSE3orAVX. This is a step towards removing the AVX hack from the X86Subtarget.h
...
llvm-svn: 147764
2012-01-09 02:28:15 +00:00
Craig Topper
744f6311d3
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
...
llvm-svn: 147762
2012-01-09 00:11:29 +00:00
Craig Topper
c1ab7afec8
Enable FISTTP* instructions when AVX is enabled.
...
llvm-svn: 147758
2012-01-08 23:04:21 +00:00
Victor Umansky
540651cf59
Reverted commit #147601 upon Evan's request.
...
llvm-svn: 147748
2012-01-08 17:20:33 +00:00
Craig Topper
f210619d08
Fix typo in the X86 backend readme. Patch from Jaeden Amero.
...
llvm-svn: 147739
2012-01-07 20:35:21 +00:00
Benjamin Kramer
6898db6269
Remove VectorExtras. This unused helper was written for a type of API that is discouraged now.
...
llvm-svn: 147738
2012-01-07 19:42:13 +00:00
Craig Topper
ca66bba45e
Remove unnecessary check of hasAVX(). It's already included in hasXMM().
...
llvm-svn: 147734
2012-01-07 18:48:43 +00:00
Eric Christopher
c206d46709
Make the 'x' constraint work for AVX registers as well.
...
Fixes rdar://10614894
llvm-svn: 147704
2012-01-07 01:02:09 +00:00
Craig Topper
29b0737452
Mark scalar FMA4 instructions as ignoring the VEX.L bit.
...
llvm-svn: 147602
2012-01-05 08:56:10 +00:00
Victor Umansky
9255b6d9fe
Peephole optimization of ptest-conditioned branch in X86 arch. Performs instruction combining of sequences generated by ptestz/ptestc intrinsics to ptest+jcc pair for SSE and AVX.
...
Testing: passed 'make check' including LIT tests for all sequences being handled (both SSE and AVX)
Reviewers: Evan Cheng, David Blaikie, Bruno Lopes, Elena Demikhovsky, Chad Rosier, Anton Korobeynikov
llvm-svn: 147601
2012-01-05 08:46:19 +00:00
Bill Wendling
ac27f0c830
Replace the uint64_t -> double convertion algorithm with one that's more efficient.
...
This small bit of ASM code is sufficient to do what the old algorithm did:
movq %rax, %xmm0
punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
#ifdef __SSE3__
haddpd %xmm0, %xmm0
#else
pshufd $0x4e, %xmm0, %xmm1
addpd %xmm1, %xmm0
#endif
It's arguably faster. One caveat, the 'haddpd' instruction isn't very fast on
all processors.
<rdar://problem/7719814>
llvm-svn: 147593
2012-01-05 02:13:20 +00:00
Benjamin Kramer
9c48f26341
Silence warnings of a mysterious compiler that still defaults to C89.
...
llvm-svn: 147553
2012-01-04 22:06:45 +00:00
Evan Cheng
104dbb0fd1
For x86, canonicalize max
...
(x > y) ? x : y
=>
(x >= y) ? x : y
So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0
This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl %esi, %edi
testl %edi, %edi
movl $0, %eax
cmovgl %edi, %eax
=>
xorl %eax, %eax
subl %esi, $edi
cmovsl %eax, %edi
rdar://10633221
llvm-svn: 147512
2012-01-04 01:41:39 +00:00
Chad Rosier
6ca97df951
Fix 80-column violations.
...
llvm-svn: 147495
2012-01-03 23:19:12 +00:00