81290f4be5
Trivial change to set UseLeaForSP flag in addition to toggling
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the FeatureLeaForSP feature bit when llvm auto detects Intel Atom.
Patch by Andy Zhang
llvm-svn: 155655
2012-04-26 19:52:27 +00:00
08ccfbe57b
Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.
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llvm-svn: 155618
2012-04-26 06:40:15 +00:00
5ff6dc34b9
Use vector_shuffles instead of target specific unpack nodes for AVX ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code.
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llvm-svn: 155537
2012-04-25 06:39:39 +00:00
810734b7f4
AVX: Add additional vbroadcast replacement sequences for integers.
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Remove the v2f64 patterns because it does not match any vbroadcast
instruction.
llvm-svn: 155461
2012-04-24 18:09:59 +00:00
7b7b99c74a
AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8
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immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.
llvm-svn: 155440
2012-04-24 11:27:53 +00:00
aa3ff8da00
AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions
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using the pattern (vbroadcast (i32load src)). In some cases, after we generate
this pattern new users are added to the load node, which prevent the selection
of the blend pattern. This commit provides fallback patterns which perform
in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1).
llvm-svn: 155437
2012-04-24 11:07:03 +00:00
0b65c40821
Remove dangling spaces. Fix some other formatting.
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llvm-svn: 155429
2012-04-24 06:36:35 +00:00
6f2a535de2
Simplify code a bit and make it compile better. Remove unused parameters.
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llvm-svn: 155428
2012-04-24 06:02:29 +00:00
3f8acfc3c4
Optimize the vector UINT_TO_FP, SINT_TO_FP and FP_TO_SINT operations where the integer type is i8 (commonly used in graphics).
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llvm-svn: 155397
2012-04-23 21:53:37 +00:00
9a0914753a
This patch fixes a problem which arose when using the Post-RA scheduler
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on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
llvm-svn: 155395
2012-04-23 21:39:35 +00:00
153bb34a3c
Use MVT instead of EVT through all of LowerVECTOR_SHUFFLEtoBlend and not just the switch. Saves a little bit of binary size.
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llvm-svn: 155339
2012-04-23 07:36:33 +00:00
0a2c809d09
Make getZeroVector and getOnesVector more alike as far as how they detect 128-bit versus 256-bit vectors. Be explicit about both sizes and use llvm_unreachable. Similar changes to getLegalSplat.
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llvm-svn: 155337
2012-04-23 07:24:41 +00:00
2bbe8bcf4e
Tidy up by removing some 'else' after 'return'
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llvm-svn: 155336
2012-04-23 06:57:04 +00:00
5c51eeecfc
Tidy up spacing in LowerVECTOR_SHUFFLEtoBlend. Remove code that checks if shuffle operand has a different type than the the shuffle result since it can never happen.
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llvm-svn: 155333
2012-04-23 06:38:28 +00:00
a52f0d09b6
Add a couple llvm_unreachables.
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llvm-svn: 155332
2012-04-23 03:42:40 +00:00
984dc015ae
Remove some tab characers.
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llvm-svn: 155331
2012-04-23 03:28:34 +00:00
ea428fd79c
Remove some 'else' after 'return'. No functional change.
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llvm-svn: 155330
2012-04-23 03:26:18 +00:00
bf7d5666f0
Make Extract128BitVector and Insert128BitVector take an unsigned instead of an ConstantNode SDValue. getConstant was almost always called just before only to have the functions take it apart and build a new ConstantSDNode.
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llvm-svn: 155325
2012-04-22 20:55:18 +00:00
2d474d6d92
Convert getNode(UNDEF) to getUNDEF.
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llvm-svn: 155321
2012-04-22 19:29:34 +00:00
860ed0d20a
Make calls to getVectorShuffle more consistent. Use shuffle VT for calls to getUNDEF instead of requerying. Use &Mask[0] instead of Mask.data().
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llvm-svn: 155320
2012-04-22 19:17:57 +00:00
43397c0900
Tidy up. 80 columns and argument alignment.
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llvm-svn: 155319
2012-04-22 18:51:37 +00:00
ad56a744f1
Simplify code by converting multiple places that were manually concatenating 128-bit vectors to use either CONCAT_VECTORS or a helper function. CONCAT_VECTORS will itself be lowered to the same pattern as before. The helper function is needed for concats of BUILD_VECTORs since getNode(CONCAT_VECTORS) will just return a large BUILD_VECTOR and we may be trying to lower large BUILD_VECTORS when this occurs.
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llvm-svn: 155318
2012-04-22 18:15:59 +00:00
8d7e56c409
ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2
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llvm-svn: 155309
2012-04-22 09:39:03 +00:00
6eadae8e60
Make some fixed arrays const. Use array_lengthof in a couple places instead of a hardcoded number.
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llvm-svn: 155294
2012-04-21 18:58:38 +00:00
2568bf3089
Tidy up. 80 columns and some other spacing issues.
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llvm-svn: 155291
2012-04-21 18:13:35 +00:00
abadc660e0
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
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llvm-svn: 155186
2012-04-20 06:31:50 +00:00
ec4bd31206
Fixed the llvm-mv X86 disassembler so the 'C' API gets jumps properly
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symbolicated. These have and operand type of TYPE_RELv which was not handled
as isBranch in translateImmediate() in X86Disassembler.cpp. rdar://11268426
llvm-svn: 155074
2012-04-18 23:12:11 +00:00
d3c9e404ba
Remove AVX vpermil intrinsics. I removed their uses from clang headers and builtins a while back.
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llvm-svn: 154985
2012-04-18 05:24:00 +00:00
354103d8ca
Don't decode vperm2i128 or vperm2f128 into a shuffle if bit 3 or 7 of the immediate is set.
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llvm-svn: 154907
2012-04-17 05:54:54 +00:00
5333e2e5ce
Temporarily turn off anti-dependency checking
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during Post RA scheduling in X86,
until the X86 target is changed to properly set up
post RA liveness.
llvm-svn: 154874
2012-04-16 22:52:28 +00:00
12da79b859
Fix incorrect atomics codegen introduced in r154705, and extend test to catch it.
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llvm-svn: 154845
2012-04-16 18:43:53 +00:00
4badeb3f0d
Replace vpermd/vpermps intrinic patterns with custom lowering to target specific nodes.
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llvm-svn: 154801
2012-04-16 07:13:00 +00:00
26d7a94981
Change type profile for vpermv back to using operand type for the mask argument to match intrinsic behavior. Add a bitcast to the lowering code to convert mask from v8i32 to v8f32 for vpermps.
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llvm-svn: 154798
2012-04-16 06:43:40 +00:00
c0075aa7ff
Flip the arguments when converting vpermd/vpermps intrinsics into instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second.
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llvm-svn: 154797
2012-04-16 06:26:15 +00:00
b86fa404d3
Merge vpermps/vpermd and vpermpd/vpermq SD nodes.
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llvm-svn: 154782
2012-04-16 00:41:45 +00:00
b04fe34030
Fix SDTypeProfile for vpermps. The mask operand should be v8i32.
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llvm-svn: 154781
2012-04-16 00:12:20 +00:00
1f8c9eb925
Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices in vpermps/vpermd. Hardware only looks at lower 3-bits.
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llvm-svn: 154780
2012-04-15 23:48:57 +00:00
bfc9a5f7d3
Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with normal shuffle vectors.
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llvm-svn: 154778
2012-04-15 22:43:31 +00:00
42bcd04ee3
Fix PR12529. The Vxx family of instructions are only supported by AVX.
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Use non-vex instructions for SSE4.
llvm-svn: 154770
2012-04-15 19:36:44 +00:00
779a72b49e
Added VPERM optimization for AVX2 shuffles
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llvm-svn: 154761
2012-04-15 11:18:59 +00:00
3e8f1f6aea
Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ~*x & y.
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llvm-svn: 154705
2012-04-13 22:47:00 +00:00
3e869f002c
Generalize r153635 to deal with TokenFactor chains; also clean up the logic and fix the tests. rdar://11069732, rdar://11236106
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llvm-svn: 154604
2012-04-12 19:14:21 +00:00
d0271b27cb
Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are integer instructions.
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llvm-svn: 154580
2012-04-12 07:23:00 +00:00
372cf15125
remove unused argument
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llvm-svn: 154494
2012-04-11 11:05:21 +00:00
9bc178ac5c
Reapply 154396 after fixing a test.
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Original message:
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendV uses a register for the selection while Vblend uses an immediate.
On sandybridge they still have the same latency and execute on the same execution ports.
llvm-svn: 154483
2012-04-11 06:40:27 +00:00
74c282b5ef
Add retw and lretw instructions. Also, fix Intel syntax parsing for all
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ret instructions.
llvm-svn: 154468
2012-04-11 01:10:53 +00:00
f7345b027a
Whitespace.
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llvm-svn: 154427
2012-04-10 19:42:07 +00:00
235a7a1746
Revert r154396, which looks to be the real culprit behind the bot failures.
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llvm-svn: 154426
2012-04-10 19:39:18 +00:00
65ada95b84
Temporarily revert this patch to see if it brings the buildbots back.
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llvm-svn: 154425
2012-04-10 19:33:16 +00:00
2735136655
Remove unused variable.
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llvm-svn: 154398
2012-04-10 15:23:13 +00:00
Preston Gurd