9c65e4d69c
Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
...
a case involving EOR, so I only added a test for ORR.
llvm-svn: 129610
2011-04-15 21:24:38 +00:00
b92fbb7036
Fix some broken links, from Matthieu Monrocq
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llvm-svn: 129609
2011-04-15 21:21:31 +00:00
d56f2d910b
Fix lines that exceed 80 columns. There is no change in functionality.
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llvm-svn: 129608
2011-04-15 21:06:38 +00:00
9fef721830
Add this test back for Darwin.
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llvm-svn: 129607
2011-04-15 21:06:27 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
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llvm-svn: 129606
2011-04-15 21:00:26 +00:00
0829b3065a
The AND instruction leaves the V flag unmodified, so it falls victim to the same
...
problem as all of the other instructions we fold with CMPs.
llvm-svn: 129602
2011-04-15 20:45:00 +00:00
7583dbdc88
Fix cmake build.
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llvm-svn: 129601
2011-04-15 20:34:45 +00:00
beb74c3f00
Some refactoring suggested by Anton Korobeynikov.
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llvm-svn: 129600
2011-04-15 20:32:03 +00:00
93eae1571c
Add missing register forms of instructions to the ARM CMP-folding code. This
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fixes <rdar://problem/9287901>.
llvm-svn: 129599
2011-04-15 20:28:28 +00:00
279169771b
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
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llvm-svn: 129594
2011-04-15 19:52:08 +00:00
a2e61292f0
Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332
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llvm-svn: 129590
2011-04-15 19:35:46 +00:00
375249a417
Add encoding tests for flds/filds
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llvm-svn: 129589
2011-04-15 19:25:31 +00:00
fad9d95722
Implements StringRef::compare with bounds. It is behaves similarly to strncmp(). Unit tests also included.
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llvm-svn: 129582
2011-04-15 17:56:50 +00:00
1af8b4dc92
Teach the SplitKit blitter to handle multiply defined values as well.
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The transferValues() function can now handle both singly and multiply defined
values, as long as the resulting live range is known. Only rematerialized values
have their live range recomputed by extendRange().
The updateSSA() function can now insert PHI values in bulk across multiple
values in multiple target registers in one pass. The list of blocks received
from transferValues() is in layout order which seems to work well for the
iterative algorithm. Blocks from extendRange() are still in reverse BFS order,
but this function is used so rarely now that it doesn't matter.
llvm-svn: 129580
2011-04-15 17:24:49 +00:00
871f70609a
Remember to set flag.
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llvm-svn: 129579
2011-04-15 17:24:46 +00:00
a01cdb0e37
Add 129518 back with a fix for when we are producing eh just because of debug info.
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Change ELF systems to use CFI for producing the EH tables. This reduces the
size of the clang binary in Debug builds from 690MB to 679MB.
llvm-svn: 129571
2011-04-15 15:11:06 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
b5e3e9dd27
Revert r129518, "Change ELF systems to use CFI for producing the EH tables. This reduces the"
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It broke several builds.
llvm-svn: 129557
2011-04-15 03:35:57 +00:00
12bb05b75b
Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't
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forget to right shift the source by 32 first. rdar://9287902
llvm-svn: 129556
2011-04-15 01:31:00 +00:00
681fef5986
For t2BFI, both Inst{26} and Inst{5} "should" be 0.
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Ref: I.1 Instruction encoding diagrams and pseudocode
llvm-svn: 129552
2011-04-15 00:35:08 +00:00
30088ba110
Add 3DNow! intrinsics.
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llvm-svn: 129551
2011-04-15 00:32:41 +00:00
421316178e
The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
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(single element or n-element structure to all lanes).
llvm-svn: 129550
2011-04-15 00:10:45 +00:00
44887f9c7e
Follow up on r127913. Fix Thumb revsh isel. rdar://9286766
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llvm-svn: 129548
2011-04-14 23:27:44 +00:00
2395626605
Add an instcombine for constructs like a | -(b != c); a select is more
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canonical, and generally leads to better code. Found while looking at
an article about saturating arithmetic.
llvm-svn: 129545
2011-04-14 22:41:27 +00:00
92651ec374
Fix an infinite alternation in JumpThreading where two transforms would repeatedly undo each other. The solution is to perform more aggressive constant folding to make one of the edges just folded away rather than trying to thread it.
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Fixes <rdar://problem/9284786>.
Discovered with CSmith.
llvm-svn: 129538
2011-04-14 21:35:50 +00:00
1cde91674a
Cleanup r129509 based on comments by Chris
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llvm-svn: 129532
2011-04-14 19:20:42 +00:00
4251b151b1
Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
...
llvm-svn: 129531
2011-04-14 19:13:28 +00:00
6f195469b1
move PR9661 out to here.
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llvm-svn: 129527
2011-04-14 18:47:18 +00:00
a519284fec
Fix another instance of the DAG combiner not using the correct type for the RHS of a shift.
...
llvm-svn: 129522
2011-04-14 17:30:49 +00:00
76b4ceb897
tests: Remove a FrontendC test which is no longer valid.
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llvm-svn: 129519
2011-04-14 15:21:16 +00:00
aa2a7cd828
Change ELF systems to use CFI for producing the EH tables. This reduces the
...
size of the clang binary in Debug builds from 690MB to 679MB.
llvm-svn: 129518
2011-04-14 15:18:53 +00:00
b88784c185
Fix whitespace and tabs.
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llvm-svn: 129517
2011-04-14 14:33:36 +00:00
0f6bad7b6e
Cleanup r129472 by using a utility routine as suggested by Eli.
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llvm-svn: 129509
2011-04-14 08:04:01 +00:00
bfbd972b1f
In the pre-RA scheduler, maintain cmp+br proximity.
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This is done by pushing physical register definitions close to their
use, which happens to handle flag definitions if they're not glued to
the branch. This seems to be generally a good thing though, so I
didn't need to add a target hook yet.
The primary motivation is to generate code closer to what people
expect and rule out missed opportunity from enabling macro-op
fusion. As a side benefit, we get several 2-5% gains on x86
benchmarks. There is one regression:
SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is
an independent scheduler bug that will be tracked separately.
See rdar://problem/9283108.
Incidentally, pre-RA scheduling is only half the solution. Fixing the
later passes is tracked by:
<rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump
Fixes:
<rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion
llvm-svn: 129508
2011-04-14 05:15:06 +00:00
d175c98d41
Documented bugpoint --compile-custom --compile-command.
...
I've used it a few times to reduce unit tests and gotten one request for information on it. It's not easy to use correctly because bugpoint doesn't tell you when you're doing it wrong.
llvm-svn: 129507
2011-04-14 05:05:36 +00:00
1d313c6f6d
add a minor missed dag combine that is blocking mid-level optimization
...
improvements, that will lead to fixing PR6627.
llvm-svn: 129504
2011-04-14 04:21:42 +00:00
493b3e72f2
sink a call into its only use.
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llvm-svn: 129503
2011-04-14 04:12:47 +00:00
fba5cdfce1
rework FoldBranchToCommonDest to exit earlier when there is a bonus
...
instruction around, reducing work.
Greatly simplify handling of debug instructions. There is no need to
build up a vector of them and then move them into the one predecessor
if we're processing a block. Instead just rescan the block and *copy*
them into the pred. If a block gets merged into multiple preds, this
will retain more debug info.
llvm-svn: 129502
2011-04-14 02:44:53 +00:00
35a65b2aa6
fix a couple -Wsign-compare warnings.
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llvm-svn: 129501
2011-04-14 02:27:25 +00:00
410ec4aad1
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
...
(movzx/movsx) because they give more information. Revert that part of the patch.
llvm-svn: 129498
2011-04-14 01:46:37 +00:00
7e07d6fb69
Have the X86 back-end emit the alias instead of what's being aliased. In most
...
cases, it's much nicer and more informative reading the alias.
llvm-svn: 129497
2011-04-14 01:11:51 +00:00
6dd69d9241
Add an option to not print the alias of an instruction. It defaults to "print
...
the alias".
llvm-svn: 129485
2011-04-13 23:36:21 +00:00
9c12834eed
During post-legalization DAG combining, be careful to only create shifts where the RHS is of the legal type for the new operation.
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llvm-svn: 129484
2011-04-13 23:22:23 +00:00
d0fb04f437
Thumb disassembler did not handle tBRIND (indirect branch) properly.
...
rdar://problem/9280370
llvm-svn: 129480
2011-04-13 21:59:01 +00:00
2e5528f0b2
Vectors with different number of elements of the same element type can have
...
the same allocation size but different primitive sizes(e.g., <3xi32> and
<4xi32>). When ScalarRepl promotes them, it can't use a bit cast but
should use a shuffle vector instead.
llvm-svn: 129472
2011-04-13 21:40:02 +00:00
b6a37bff21
Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).
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rdar://problem/9280470
llvm-svn: 129471
2011-04-13 21:35:49 +00:00
ffa6378fd6
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
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rdar://problem/9279440
llvm-svn: 129469
2011-04-13 21:04:32 +00:00
415b5e8341
Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
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llvm-svn: 129468
2011-04-13 21:01:19 +00:00
aabc142fce
Fix format string warning.
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llvm-svn: 129467
2011-04-13 20:41:43 +00:00
9398197ef1
Fix a regression caused by r102515 where explicit alignment on globals is
...
ignored. There was a test to catch this, but it was just blindly updated in
a large change. This fixes another part of <rdar://problem/9275290>.
llvm-svn: 129466
2011-04-13 20:36:04 +00:00
Cameron Zwarich