2d91a4fd6a
Add missing const qualifiers.
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llvm-svn: 37342
2007-05-29 18:42:18 +00:00
1d764eca98
Hooks for predication support.
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llvm-svn: 37308
2007-05-23 07:22:05 +00:00
8c8afb27d7
Fix some -march=thumb regressions. tBR_JTr is not predicable.
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llvm-svn: 37272
2007-05-21 23:17:32 +00:00
147b334b6a
BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.
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llvm-svn: 37268
2007-05-21 18:56:31 +00:00
e20dd92792
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
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llvm-svn: 37193
2007-05-18 00:18:17 +00:00
dcff2eb0e8
PredicateInstruction returns true if the operation was successful.
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llvm-svn: 37124
2007-05-16 21:53:07 +00:00
e2762c3d68
Removed isPredicable().
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llvm-svn: 37119
2007-05-16 20:50:23 +00:00
ad3aac71ce
Hooks for predication support.
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llvm-svn: 37093
2007-05-16 02:01:49 +00:00
0f7cbe8370
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
4a00cf3fc4
Rewrite of Thumb constant islands handling (exact allowance for padding
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around islands and jump tables).
llvm-svn: 36573
2007-04-29 19:19:30 +00:00
910c80851e
Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.
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llvm-svn: 36483
2007-04-26 19:00:32 +00:00
8cd224e81c
Relex assertions to account for additional implicit def / use operands.
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llvm-svn: 36430
2007-04-25 07:12:14 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
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target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
e8315fe3f5
Inverted logic.
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llvm-svn: 35619
2007-04-03 06:44:25 +00:00
7dbbd00b06
findRegisterUseOperand() changed.
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llvm-svn: 35366
2007-03-26 22:41:48 +00:00
9bb01c9f4f
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ec13f826a2
Spill / restore should avoid modifying the condition register.
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llvm-svn: 33971
2007-02-07 00:06:56 +00:00
95b85e34ff
Copy and paste bug.
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llvm-svn: 33658
2007-01-30 08:22:33 +00:00
ce8fa3ed83
Misseed thumb jumptable branch.
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llvm-svn: 33656
2007-01-30 08:03:06 +00:00
760c68b8af
Factor GetInstSize() out of constpool island pass.
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llvm-svn: 33644
2007-01-29 23:45:17 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
ed32883b27
fix warning about missing newline at end of file
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llvm-svn: 31162
2006-10-24 17:07:11 +00:00
aaeede0aa2
implement uncond branch insertion, mark branches with isBranch.
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llvm-svn: 31160
2006-10-24 16:47:57 +00:00
3130a756ef
add shifts to addressing mode 1
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llvm-svn: 30291
2006-09-13 12:09:43 +00:00
e45a79a9e2
partial implementation of the ARM Addressing Mode 1
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llvm-svn: 30252
2006-09-11 17:25:40 +00:00
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
27f8bdc7e5
implement minimal versions of
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ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr
llvm-svn: 28431
2006-05-23 02:48:20 +00:00
ffdc24b847
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
Evan Cheng