Commit Graph

288266 Commits

Author SHA1 Message Date
Haicheng Wu b09308d82a [GlobalMerge] Fix a typo
now => know

llvm-svn: 330965
2018-04-26 17:56:50 +00:00
Vlad Tsyrklevich b768d235a9 Revert "Enable EliminateAvailableExternally pass for -O1"
This reverts commit r330961 because it breaks a handful of clang tests.

llvm-svn: 330964
2018-04-26 17:54:53 +00:00
Paul Semel b492494c0f [llvm-objcopy] Add --localize-symbol option
llvm-svn: 330963
2018-04-26 17:44:43 +00:00
Vlad Tsyrklevich 3b59a8aba0 Update stale comment in AsmWriter.cpp
Summary:
The old comment referred to llvm/IR/Writer.h which doesn't longer exist.
This patch replaces it with an up-to-date description of AsmWriter library.

Patch by Alex Yursha.

Reviewers: gribozavr, vlad.tsyrklevich

Reviewed By: vlad.tsyrklevich

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45895

llvm-svn: 330962
2018-04-26 17:34:51 +00:00
Vlad Tsyrklevich 42c5a9c29a Enable EliminateAvailableExternally pass for -O1
Summary:
Follow-up to D43690, the EliminateAvailableExternally pass currently
runs under -O0 and -O2 and up. Under -O1 we would still want to drop
available_externally symbols to reduce space without inlining having
run.

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: mehdi_amini, llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D46093

llvm-svn: 330961
2018-04-26 17:33:24 +00:00
Rafael Espindola 06cb7c8773 Simplify processRelocAux.
It returns a different Expr only in the case of creating a function
symbol pointing to its plt entry. We can just add a call to
addPltEntry to avoid that and return void.

With this patch further simplifications of how we handle copy
relocations are possible.

llvm-svn: 330960
2018-04-26 17:22:44 +00:00
Sam Clegg 8c4b0ce2b1 [WebAssembly] objdump: Don't assume all relocations have symbols
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D46134

llvm-svn: 330959
2018-04-26 17:05:04 +00:00
Sanjay Patel c5ded68077 [docs] provide the specific sanitizer option to detect junk-in-the-ftrunc
llvm-svn: 330958
2018-04-26 17:04:07 +00:00
Sam Clegg f676cdd515 [WebAssembly] Implement getRelocationValueString()
And use it in llvm-objdump.

Differential Revision: https://reviews.llvm.org/D46092

llvm-svn: 330957
2018-04-26 16:41:51 +00:00
Simon Dardis f760b2c087 [mips] Fix a test case which is keeping the expensive checks bot win red (NFC)
llvm-svn: 330956
2018-04-26 16:22:47 +00:00
Marshall Clow 57e782535e Move old test into test/libcxx, and implement new version of test for ostreambuf_iterator::failed. Fixes PR#37245. Thanks to Billy O'Neill for the bug report.
llvm-svn: 330955
2018-04-26 16:16:45 +00:00
Mark Searles 2a19af6e17 [AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
Differential Revision: https://reviews.llvm.org/D46067

llvm-svn: 330954
2018-04-26 16:11:19 +00:00
Rafael Espindola f4a9d56a9a Delete GotPltIndex.
It was always an offset of PltIndex.

This doesn't reduce the size of the structures, but makes it easier to
do so in a followup patch.

llvm-svn: 330953
2018-04-26 16:09:30 +00:00
Simon Dardis 8086b9db3d [mips] Correct the definitions of some control instructions
Correct the definitions of ei, di, eret, deret, wait, syscall and break.
Also provide microMIPS specific aliases to match the MIPS aliases.

Additionally correct the definition of the wait instruction so that
it is present in the instruction mapping tables.

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D45939

llvm-svn: 330952
2018-04-26 16:06:34 +00:00
Sanjay Patel 5a90285bd9 [DAGCombiner] limit ftrunc optimizations with function attribute
As noted, the attribute name is subject to change once we have
the clang side implemented, but it's clear that we need some
kind of attribute-based predication here based on the discussion
for:
rL330437

llvm-svn: 330951
2018-04-26 16:04:44 +00:00
Sanjay Patel 99a5f396d4 [x86] add tests to show potential opt-out of ftrunc optimization; NFC
This is another preliminary step for disabling this transform as 
discussed in the post-commit thread for:
rL330437
I'm using one of the names suggested there for the attribute, but 
we can fix that up as needed once the clang side of this is sorted 
out. 

llvm-svn: 330950
2018-04-26 15:36:15 +00:00
Alex Bradbury fda6037e98 [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
This causes some slight shuffling but no meaningful codegen differences on the 
corpus I used for testing, but it has a larger impact when combined with e.g. 
rematerialisation. Regardless, it makes sense to report as accurate 
target-specific information as possible.

llvm-svn: 330949
2018-04-26 15:34:27 +00:00
Benjamin Kramer 7dd437710e [NVPTX] Make the legalizer expand shufflevector of <2 x half>
There's no direct instruction for this, but it's trivially implemented
with two movs. Without this the code generator just dies when
encountering a shufflevector.

Differential Revision: https://reviews.llvm.org/D46116

llvm-svn: 330948
2018-04-26 15:26:29 +00:00
Sanjay Patel a5da086386 [DAGCombiner] refactor FP->int->FP folds; NFC
As discussed in the post-review comments for rL330437,
we need to guard this fold to allow existing code to
keep working with the undefined behavior that they've
come to rely on.

That would mean duplicating more code than we already 
have, so let's fix that first. 

llvm-svn: 330947
2018-04-26 15:20:18 +00:00
Yuka Takahashi 4f38ffa63c Add getDeserializationListener to ASTReader
Summary:
We need to know if ASTReader already has a DeserializationListner or
not, and this also helps to create a multiplexing deserialization
listener if there is one already attached.

Reviewers: v.g.vassilev, rsmith, dblaikie, thakis

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D45921

llvm-svn: 330946
2018-04-26 15:09:13 +00:00
Matthew Simpson cfdec0ff70 [SLP] Add tests for transposable binary operations
These test cases are vectorizable, but we are currently unable to vectorize
them effectively.

llvm-svn: 330945
2018-04-26 14:50:04 +00:00
Guansong Zhang ad6c26516b [OpenMP] Remove compilation warning when using clang to compile bc files.
Summary: Minor printf format correction. NVCC ignore those. Clang will give warning on these if debug is enabled.

Reviewers: grokos

Reviewed By: grokos

Subscribers: openmp-commits

Tags: #openmp

Differential Revision: https://reviews.llvm.org/D45528

llvm-svn: 330944
2018-04-26 14:06:53 +00:00
Alex Bradbury 15e894baee [RISCV] Implement isZextFree
This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected
and avoiding unnecessary masks.

llvm-svn: 330943
2018-04-26 14:04:18 +00:00
Alex Bradbury e74f519241 [RISCV] Add test case showing suboptimal codegen when loading unsigned char/short
Implementing isZextFree will allow lbu or lhu to be selected rather than 
lb+mask and lh+mask.

llvm-svn: 330942
2018-04-26 14:00:35 +00:00
Matthew Simpson b4096ebe26 [TTI, AArch64] Add transpose shuffle kind
This patch adds a new shuffle kind useful for transposing a 2xn matrix. These
transpose shuffle masks read corresponding even- or odd-numbered vector
elements from two n-dimensional source vectors and write each result into
consecutive elements of an n-dimensional destination vector. The transpose
shuffle kind is meant to model the TRN1 and TRN2 AArch64 instructions. As such,
this patch also considers transpose shuffles in the AArch64 implementation of
getShuffleCost.

Differential Revision: https://reviews.llvm.org/D45982

llvm-svn: 330941
2018-04-26 13:48:33 +00:00
Alex Bradbury 130b8b3f2b [RISCV] Implement isTruncateFree
Adapted from ARM's implementation introduced in r313533 and r314280.

llvm-svn: 330940
2018-04-26 13:37:00 +00:00
Lama Saba a331f91853 [X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
Differential Revision: https://reviews.llvm.org/D45823

Change-Id: Icf6f34f6babc3cb2ff5292fde003472473037a71
llvm-svn: 330939
2018-04-26 13:16:11 +00:00
Alex Bradbury dcbff63c24 [RISCV] Implement isLegalICmpImmediate
I'm unable to construct a representative test case that demonstrates the 
advantage, but it seems sensible to report accurate target-specific 
information regardless.

llvm-svn: 330938
2018-04-26 13:15:17 +00:00
Alex Bradbury 5c41ecedf8 [RISCV] Implement isLegalAddImmediate
This causes a trivial improvement in the recently added lsr-legaladdimm.ll 
test case.

llvm-svn: 330937
2018-04-26 13:00:37 +00:00
Alex Bradbury c2f78f80da [RISCV] Add test/CodeGen/RISCV/lsr-legaladdimm.ll
Add a test case which will show a codegen difference upon the implementation 
of a target-specific isLegalAddImmediate.

llvm-svn: 330936
2018-04-26 12:57:29 +00:00
Andrea Di Biagio 38fe227fd9 [Tablegen] Simplify code in CodeGenSchedule. NFCI
llvm-svn: 330935
2018-04-26 12:56:26 +00:00
Sander de Smalen fe17a78b86 [AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's 
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling 
the immediate is out of range when it actually parsed a register.

Patch [2/2] in a series to improve assembler diagnostics for SVE:
-  Patch [1/2]: https://reviews.llvm.org/D45879
-  Patch [2/2]: https://reviews.llvm.org/D45880

Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D45880

llvm-svn: 330934
2018-04-26 12:54:42 +00:00
Benjamin Kramer bd89647229 [NVPTX] Deduplicate code. No functionality change.
llvm-svn: 330933
2018-04-26 12:30:16 +00:00
Alex Bradbury 09926296df [RISCV] Implement isLegalAddressingMode for RISC-V
This has no impact on codegen for the current RISC-V unit tests or my small 
benchmark set and very minor changes in a few programs in the GCC torture 
suite. Based on this, I haven't been able to produce a representative test 
program that demonstrates a benefit from isLegalAddressingMode. I'm committing 
the patch anyway, on the basis that presenting accurate information to the 
target-independent code is preferable to relying on incorrect generic 
assumptions.

llvm-svn: 330932
2018-04-26 12:13:48 +00:00
Florian Hahn fd2bc11248 [LoopInterchange] Ignore debug intrinsics during legality checks.
Reviewers: aprantl, mcrosier, karthikthecool

Reviewed By: aprantl

Subscribers: mattd, vsk, #debug-info, llvm-commits

Differential Revision: https://reviews.llvm.org/D45379

llvm-svn: 330931
2018-04-26 10:26:17 +00:00
Sander de Smalen a2fb1d18d2 [AsmMatcher] Extend PredicateMethod with optional DiagnosticPredicate
An optional, light-weight and backward-compatible mechanism to allow
specifying that a diagnostic _only_ applies to a partial mismatch (NearMiss),
rather than a full mismatch.

Patch [1/2] in a series to improve assembler diagnostics for SVE.
-  Patch [1/2]: https://reviews.llvm.org/D45879
-  Patch [2/2]: https://reviews.llvm.org/D45880

Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar

Reviewed By: olista01

Differential Revision: https://reviews.llvm.org/D45879

llvm-svn: 330930
2018-04-26 09:24:45 +00:00
Sander de Smalen 466410b3fd [AArch64][SVE] Asm: Negative tests for all LD1 gather (scalar+vector) load instructions.
Patch [3/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D45958

llvm-svn: 330929
2018-04-26 08:43:22 +00:00
Sander de Smalen 74f9e6720b [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions.
Patch [2/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D46023

llvm-svn: 330928
2018-04-26 08:19:53 +00:00
Serge Pavlov db31e7a582 Make test more platform neutral
llvm-svn: 330927
2018-04-26 08:08:25 +00:00
Serge Pavlov f015a56761 [ConfigFiles] Update argument strings when merging argrument lists
Implementation of `InputArgList` assumes its field `ArgStrings` contains
strings for each argument exactly in the same order. This condition was
broken when arguments from config file and from invocation were merged.

This change fixes https://bugs.llvm.org/show_bug.cgi?id=37196 (Clang
config files can crash argument handling).

llvm-svn: 330926
2018-04-26 06:28:47 +00:00
Rafael Espindola faa3b8a554 Add a test. NFC.
This would have fund a bug in a patch I am working on.

llvm-svn: 330925
2018-04-26 06:10:18 +00:00
Shoaib Meenai fd7befad23 [cmake] Make linker detection take flags into account
LLVM might be compiled using a toolchain file which controls the linker
to use via flags (e.g. `-B` or `-fuse-ld=`). Take these flags into
account for linker detection. We can also correct the detection by
manually passing LLVM_USE_LINKER, of course, but it seems more
convenient to have the detection take flags into account.

Differential Revision: https://reviews.llvm.org/D45464

llvm-svn: 330924
2018-04-26 06:04:46 +00:00
Craig Topper e95bde33df [X86] Add support for _mm512_mullox_epi64 and _mm512_mask_mullox_epi64 intrinsics to match icc.
On AVX512F targets we'll produce an emulated sequence using 3 pmuludqs with shifts and adds. On AVX512DQ we'll use vpmulld.

Fixes PR37140.

llvm-svn: 330923
2018-04-26 05:38:39 +00:00
Craig Topper bc26f3b61b [X86] Print 'tbyte ptr' instead of 'xword ptr' for f80mem in Intel syntax.
This matches objdump.

llvm-svn: 330922
2018-04-26 05:07:40 +00:00
Craig Topper b0227189fd [X86] Remove alignment restriction on loading folding of pcmp[ei]str* during isel too.
This is a follow up to the changes in r330896 which enabled folding after isel during peephole and register allocation.

llvm-svn: 330897
2018-04-26 03:53:39 +00:00
Chandler Carruth eb631ef51e [x86] Allow folding unaligned memory operands into pcmp[ei]str*
instructions.

These have special permission according to the x86 manual to read
unaligned memory, and this folding is done by ICC and GCC as well.

This corrects one of the issues identified in PR37246.

llvm-svn: 330896
2018-04-26 03:17:25 +00:00
Chandler Carruth 8cc8c0a87c [x86] NFC: Add tests for idiomatic usage patterns of SSE4.2 string
comparison instructions (pcmp[ei]stri*).

These will help show improvements from fixes to PR37246.

I've not really covered the mask forms of this intrinsic as I don't have
as good of an intuition about the likely usage patterns there. Happy for
someone to extend this with tests covering the mask form.

llvm-svn: 330895
2018-04-26 03:12:17 +00:00
Richard Smith 04100943da Diagnose missing template arguments for a variable template even when there is
a preceding 'template' keyword.

We only diagnose in the dependent case (wherein we used to crash). Another bug
prevents the diagnostic from appearing in the non-template case.

llvm-svn: 330894
2018-04-26 02:10:22 +00:00
Max Kazantsev 2c287ec9c5 Revert "[SCEV] Make computeExitLimit more simple and more powerful"
This reverts commit 023c8be90980e0180766196cba86f81608b35d38.

This patch triggers miscompile of zlib on PowerPC platform. Most likely it is
caused by some pre-backend PPC-specific pass, but we don't clearly know the
reason yet. So we temporally revert this patch with intention to return it
once the problem is resolved. See bug 37229 for details.

llvm-svn: 330893
2018-04-26 02:07:40 +00:00
Rui Ueyama b774c3c0e5 Simplify. NFC.
llvm-svn: 330892
2018-04-26 01:38:29 +00:00