Commit Graph

286433 Commits

Author SHA1 Message Date
Artem Dergachev d1fe360b06 [analyzer] Fix test triple in missing-bind-temporary.cpp.
Otherwise the default triple for x86-windows-msvc2015 auto-inserts
__attribute__((thiscall)) to some calls.

Fixes the respective buildbot.

llvm-svn: 328903
2018-03-30 21:22:35 +00:00
Rumeet Dhindsa 7588a8e89d Initialize Elf Header to zero to ensure that bytes not assigned any value later on are initialized properly.
Differential Revision: https://reviews.llvm.org/D44986

llvm-svn: 328902
2018-03-30 20:49:34 +00:00
Jacob Gravelle 40926451d2 [WebAssembly] Register wasm passes with the PassRegistry
Summary:
This exposes WebAssembly passes for use on the command line (as
arguments to -print-before and the like).

Reviewers: dschuff, sunfish

Subscribers: MatzeB, jfb, sbc100, llvm-commits, aheejin

Differential Revision: https://reviews.llvm.org/D45103

llvm-svn: 328901
2018-03-30 20:36:58 +00:00
Jonathan Peyton 1e6bb8d5de Minor cleanup in __kmp_atfork_child()
This change removes the unnecessary lock operation on __kmp_initz_lock inside
the __kmp_atfork_child() function for Linux; the lock variable is initialized
in the same function later.

Patch by Hansang Bae

Differential Revision: https://reviews.llvm.org/D44949

llvm-svn: 328900
2018-03-30 19:55:11 +00:00
Krzysztof Parzyszek 526fbf8e33 [Hexagon] Fix testcase
llvm-svn: 328899
2018-03-30 19:46:28 +00:00
Krzysztof Parzyszek 74096f7258 [Hexagon] Reduce excessive indentation in .s output
llvm-svn: 328898
2018-03-30 19:30:28 +00:00
Krzysztof Parzyszek 0f983d69a4 [Hexagon] Avoid creating invalid offsets in packetizer
Two memory instructions with a dependency only on the address register
between the two (the first one of them being post-incrememnt) can be
packetized together after the offset on the second was updated to the
incremement value. Make sure that the new offset is valid for the
instruction.

llvm-svn: 328897
2018-03-30 19:28:37 +00:00
Artem Dergachev 95f9a68b1f [analyzer] Track null or undef values through pointer arithmetic.
Pointer arithmetic on null or undefined pointers results in null or undefined
pointers. This is obvious for undefined pointers; for null pointers it follows
from our incorrect-but-somehow-working approach that declares that 0 (Loc)
doesn't necessarily represent a pointer of numeric address value 0, but instead
it represents any pointer that will cause a valid "null pointer dereference"
issue when dereferenced.

For now we've been seeing through pointer arithmetic at the original dereference
expression, i.e. in bugreporter::getDerefExpr(), but not during further
investigation of the value's origins in bugreporter::trackNullOrUndefValue().
The patch fixes it.

Differential Revision: https://reviews.llvm.org/D45071

llvm-svn: 328896
2018-03-30 19:27:42 +00:00
Artem Dergachev 6a5cd5e1ca [CFG] [analyzer] Work around a disappearing CXXBindTemporaryExpr.
Sometimes template instantiation causes CXXBindTemporaryExpr to be missing in
its usual spot. In CFG, temporary destructors work by relying on
CXXBindTemporaryExprs, so they won't work in this case.

Avoid the crash and notify the clients that we've encountered an unsupported AST
by failing to provide the ill-formed construction context for the temporary.

Differential Revision: https://reviews.llvm.org/D44955

llvm-svn: 328895
2018-03-30 19:25:39 +00:00
Davide Italiano b5294a3b59 [lldb-dotest] Don't swallow error exit codes.
llvm-svn: 328894
2018-03-30 19:24:08 +00:00
Artem Dergachev 9d3a7d8b2b [CFG] [analyzer] Avoid modeling C++17 constructors that aren't fully supported.
Not enough work has been done so far to ensure correctness of construction
contexts in the CFG when C++17 copy elision is in effect, so for now we
should drop construction contexts in the CFG and in the analyzer when
they seem different from what we support anyway.

This includes initializations with conditional operators and return values
across multiple stack frames.

Differential Revision: https://reviews.llvm.org/D44854

llvm-svn: 328893
2018-03-30 19:21:18 +00:00
Andrea Di Biagio dc97172b2f [X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts and
VSQRT instructions.

There were still a few AVX instructions with an incorrect number of opcodes.
These should be fixed now.

llvm-svn: 328892
2018-03-30 18:53:47 +00:00
Eli Friedman 1ad23a494b Remove unused CHECK lines leftover from r306928.
The RUN lines were removed, but the corresponding CHECK lines never
went away.

llvm-svn: 328891
2018-03-30 18:39:28 +00:00
Peter Collingbourne d03bf12c1b DataFlowSanitizer: wrappers of functions with local linkage should have the same linkage as the function being wrapped
This patch resolves link errors when the address of a static function is taken, and that function is uninstrumented by DFSan.

This change resolves bug 36314.

Patch by Sam Kerner!

Differential Revision: https://reviews.llvm.org/D44784

llvm-svn: 328890
2018-03-30 18:37:55 +00:00
Peter Collingbourne 5e3ee94562 ELF: Try to create last thunk section at ThunkSectionSpacing bytes before the end.
Now that we have the ability to create short thunks, it is beneficial
for thunk sections to be surrounded by ThunkSectionSpacing bytes
of code on both sides in order to increase the likelihood that the
distance from the thunk to the target will be sufficiently small to
allow for the creation of a short thunk. This is currently the case
for most thunks that we create, except for the last one, which could,
depending on the size of the output section, potentially appear near
the end and therefore have a relatively small amount of code after it.

This patch moves the last thunk section to ThunkSectionSpacing bytes
before the end of the output section, as long as the section is larger
than 2*ThunkSectionSpacing bytes. It reduces the size of Chromium
for Android's .text section by 32KB.

Differential Revision: https://reviews.llvm.org/D44966

llvm-svn: 328889
2018-03-30 18:32:24 +00:00
Alexey Bataev 03f270c900 [OPENMP] Added emission of offloading data sections for declare target
variables.

Added emission of the offloading data sections for the variables within
declare target regions + fixes emission of the declare target variables
marked as declare target not within the declare target region.

llvm-svn: 328888
2018-03-30 18:31:07 +00:00
Puyan Lotfi 399b46c98d [MIR] Adding support for Named Virtual Registers in MIR.
llvm-svn: 328887
2018-03-30 18:15:54 +00:00
Andrea Di Biagio 3eaa26bb64 [X86][BtVer2] Fix the number of uOps for horizontal operations.
llvm-svn: 328886
2018-03-30 18:15:30 +00:00
Tim Shen 8f9f026965 [NVPTX] Enable StructuredCFG for NVPTX
Summary:
Make NVPTX require structured CFG. Added a temporary flag to
"roll back" the behavior for easy deployment.

Combined with D45008, this fixes several internal Nvidia GPU test
failures that we suspect to be ptxas miscompiles (PR27738).

Reviewers: jlebar

Subscribers: jholewinski, sanjoy, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D45070

llvm-svn: 328885
2018-03-30 17:51:03 +00:00
Tim Shen 1a8c6776a3 [BlockPlacement] Disable block placement tail duplciation in structured CFG.
Summary:
Tail duplication easily breaks the structure of CFG, e.g. duplicating on
a region entry. If the structure is intended to be preserved, then we
may want to configure tail duplication, or disable it for structured
CFG. From our benchmark results disabling it doesn't cause performance
regression.

Notice that this currently affects AMDGPU backend. In the next patch, I
also plan to turn on requiresStructuredCFG for NVPTX.

All unit tests still pass.

Reviewers: jlebar, arsenm

Subscribers: jholewinski, sanjoy, wdng, tpr, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D45008

llvm-svn: 328884
2018-03-30 17:51:00 +00:00
Robert Widmann 478fce9ebf [LLVM-C] Finish exception instruction bindings - Round 2
Summary:
Previous revision caused a leak in the echo test that got caught by the ASAN bots because of missing free of the handlers array and was reverted in r328759.  Resubmitting the patch with that correction.

Add support for cleanupret, catchret, catchpad, cleanuppad and catchswitch and their associated accessors.

Test is modified from SimplifyCFG because it contains many diverse usages of these instructions.

Reviewers: whitequark, deadalnix

Reviewed By: whitequark

Subscribers: llvm-commits, vlad.tsyrklevich

Differential Revision: https://reviews.llvm.org/D45100

llvm-svn: 328883
2018-03-30 17:49:53 +00:00
Rui Ueyama 5f8c3e85aa Fix Windows buildbots.
llvm-svn: 328882
2018-03-30 17:49:51 +00:00
Zachary Turner ce5b834abf Fix some signed / unsigned conversion problems.
llvm-svn: 328881
2018-03-30 17:28:35 +00:00
Rui Ueyama 5aab635e10 Improve error message for an unknown --plugin-opt.
Before:

  $ ld.lld --plugin-opt=-foo
  ld.lld: --Unknown command line argument '-abc'

After:

  $ ld.lld --plugin-opt=-foo
  ld.lld: --plugin-opt: ld.lld --Unknown command line argument '-abc'

Differential Revision: https://reviews.llvm.org/D45075

llvm-svn: 328880
2018-03-30 17:22:44 +00:00
Nico Weber a764379458 [lld-link] Add comment explaining that /FIXED behavior is correct despite contradicting MSDN.
Also add a test for /FIXED.
https://reviews.llvm.org/D45087

llvm-svn: 328879
2018-03-30 17:17:04 +00:00
Zachary Turner d5cf5cf637 [llvm-pdbutil] Dig deeper into the PDB and DBI streams when explaining.
This will show more detail when using `llvm-pdbutil explain` on an
offset in the DBI or PDB streams.  Specifically, it will dig into
individual header fields and substreams to give a more precise
description of what the byte represents.

llvm-svn: 328878
2018-03-30 17:16:50 +00:00
Nico Weber 0945ad6643 [lld-link] Let /PROFILE imply /OPT:REF /OPT:NOICF /INCREMENTAL:NO /FIXED:NO
/FIXED:NO is always the default, so that part needs no work.

Also test the interaction of /ORDER: with /INCREMENTAL.

https://reviews.llvm.org/D45091

llvm-svn: 328877
2018-03-30 17:14:50 +00:00
Derek Schuff a2726e9ab6 [WebAssembly] Refactor tablegen for store instructions (NFC)
Summary: Add patterns similar to loads.

Differential Revision: https://reviews.llvm.org/D45064

llvm-svn: 328876
2018-03-30 17:02:50 +00:00
Krzysztof Parzyszek fce30c2ba3 Revert "peel loops with runtime small trip counts"
This reverts commit r328854, it breaks some Hexagon tests.

llvm-svn: 328875
2018-03-30 16:55:44 +00:00
Stanislav Mekhanoshin 74e2974ac6 [AMDGPU] Fixed some instructions latencies
Differential Revision: https://reviews.llvm.org/D45073

llvm-svn: 328874
2018-03-30 16:19:13 +00:00
Rui Ueyama 0961218c10 [WebAssembly] Error if both --export-table and --import-table are specified.
Differential Revision: https://reviews.llvm.org/D45001

llvm-svn: 328873
2018-03-30 16:06:14 +00:00
Sanjay Patel e09b7dcf3d [SelectionDAG] Removing FABS folding from DAGCombiner
The code has bugs dealing with -0.0.

Since D44550 introduced FABS pattern folding in InstCombine, 
this patch removes the now-redundant code that causes 
https://bugs.llvm.org/show_bug.cgi?id=36600.

Patch by Mikhail Dvoretckii!

Differential Revision: https://reviews.llvm.org/D44683

llvm-svn: 328872
2018-03-30 15:42:52 +00:00
Ben Hamilton 4dc1cdc5e1 [clang-format] Ensure wrapped ObjC selectors with 1 arg obey IndentWrappedFunctionNames
Summary:
In D43121, @Typz introduced logic to avoid indenting 2-or-more
argument ObjC selectors too far to the right if the first component
of the selector was longer than the others.

This had a small side effect of causing wrapped ObjC selectors with
exactly 1 argument to not obey IndentWrappedFunctionNames:

```
- (aaaaaaaaaa)
aaaaaaaaaa;
```

This diff fixes the issue by ensuring we align wrapped 1-argument
ObjC selectors correctly:

```
- (aaaaaaaaaa)
    aaaaaaaaaa;
```

Test Plan: New tests added. Test failed before change, passed
  after change. Ran tests with:
  % make -j12 FormatTests && ./tools/clang/unittests/Format/FormatTests

Reviewers: djasper, klimek, Typz, jolesiak

Reviewed By: djasper, jolesiak

Subscribers: cfe-commits, Typz

Differential Revision: https://reviews.llvm.org/D44994

llvm-svn: 328871
2018-03-30 15:38:45 +00:00
Krzysztof Parzyszek 4f99836a9e [Hexagon] Recognize and handle :endloop01
llvm-svn: 328870
2018-03-30 15:29:47 +00:00
Krzysztof Parzyszek 46abcb236b [Hexagon] Fix printing :mem_noshuf on compiler-generated packets
llvm-svn: 328869
2018-03-30 15:09:05 +00:00
Krzysztof Parzyszek 71731fab24 [Hexagon] Fix flags for store-related intrinsics
llvm-svn: 328868
2018-03-30 14:57:01 +00:00
Andrea Di Biagio 073a9d74ca [X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds and
most vector logic instructions.

Fixed a few InstRW that forgot to specify a ReadAfterLd for the register input
operand.

llvm-svn: 328867
2018-03-30 14:48:08 +00:00
Krzysztof Parzyszek 3f55ad8fae [Hexagon] Remove unused scheduling classes
llvm-svn: 328866
2018-03-30 14:34:32 +00:00
Andrea Di Biagio 42d8ea22c0 [X86][BtVer2] Add tests that show how ReadAfterLd is missing for some
instructions.

In the Btver2 model, there are a few InstRW overrides that don't specify a
ReadAfterLd for the register input operand.

As a result, a few AVX variants of horizontal operations and most vector logic
operations with a folded memory operand don't have a ReadAdvance info associated
to their input register operands.

llvm-svn: 328865
2018-03-30 14:29:33 +00:00
Krzysztof Parzyszek 1ca23d9837 [Hexagon] Pass pointer to SelectionDAG to dump functions
llvm-svn: 328864
2018-03-30 14:29:15 +00:00
Nico Weber 8ee3b06f82 Simplify test more.
llvm-svn: 328863
2018-03-30 13:48:11 +00:00
Nico Weber 4fb8799f74 Simplify test.
As of rL215127, FileCheck has an -allow-empty flag,
so this could be used instead of writing a dummy line.
But it looks like the log is never empty now, so not
even that is needed.

llvm-svn: 328862
2018-03-30 13:44:15 +00:00
Andrea Di Biagio 01043625cf [X86] Add llvm-mca tests for r328834.
Verify that the ReadAfterLd is correctly applied to FMA and 4-ops variable blend
instructions.

As Craig pointed out in D44726, some Intel models still have to be fixed.

llvm-svn: 328861
2018-03-30 13:38:37 +00:00
Henry Wong f1a0ff755a [analyzer] Remove the unused method declaration in `ValistChecker.cpp`.
Summary: `getVariableNameFromRegion()` seems useless.

Reviewers: xazax.hun, george.karpenkov

Reviewed By: xazax.hun

Subscribers: szepet, rnkovacs, a.sidorin, cfe-commits, MTC

Differential Revision: https://reviews.llvm.org/D45081

llvm-svn: 328860
2018-03-30 13:37:50 +00:00
Andrea Di Biagio 0823090843 [X86] Add tests to verify the presence of "ReadAfterLd" after r328823.
This change adds a couple of tests to verify the change introduced by revision
328823 ([X86] Correct the placement of ReadAfterLd in BEXTR and BZHI).

llvm-svn: 328859
2018-03-30 11:44:48 +00:00
Vlad Tsyrklevich 894c028d56 Revert "[LLVM-C] Finish exception instruction bindings"
This reverts commit r328759. It was causing LSan failures on sanitizer-x86_64-linux-bootstrap

llvm-svn: 328858
2018-03-30 06:21:28 +00:00
Bruno Cardoso Lopes 7d29486ddd [Modules] Improve fixit for framework private module maps
The wrong source range was being provided in some case, fix that to get
a better fixit.

rdar://problem/38520199

llvm-svn: 328857
2018-03-30 05:17:58 +00:00
Michael Bedy 59e5ef793c [AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE.
Summary:
The phase attempts to transform operations that extract a portion of a value
into an SDWA src operand in cases where that value is used only once. It
was not prepared for this use to be the preserved portion of a value for
dst:UNUSED_PRESERVE, resulting in a crash or assert.

This change either rejects the illegal SDWA attempt, or in the case where
dst:WORD_1 and the src_sel would be WORD_0, removes the unneeded
extract instruction.

Reviewers: arsenm, #amdgpu

Reviewed By: arsenm, #amdgpu

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D44364

llvm-svn: 328856
2018-03-30 05:03:36 +00:00
Ikhlas Ajbar a7d614c3e5 [Hexagon] add missing lit config file
llvm-svn: 328855
2018-03-30 03:32:24 +00:00
Ikhlas Ajbar 66c8ba5a50 peel loops with runtime small trip counts
For Hexagon, peeling loops with small runtime trip count is beneficial for our
benchmarks. We set PeelCount in HexagonTargetInfo.cpp and we use PeelCount set
by the target for computing the desired peel count.

Differential Revision: https://reviews.llvm.org/D44880

llvm-svn: 328854
2018-03-30 03:05:34 +00:00