b792f844ad
Update the insert position after scheduling, which may change the
...
position when emitting multiple blocks when executing a custom
inserter.
llvm-svn: 107797
2010-07-07 18:22:13 +00:00
637ee5f149
Update comment.
...
llvm-svn: 107796
2010-07-07 18:18:18 +00:00
769201448d
Fix debugging strings.
...
llvm-svn: 107795
2010-07-07 17:28:45 +00:00
24556940ee
Issue the warning about being slow whenever optimization is disabled,
...
and not just for Debug+Asserts builds.
llvm-svn: 107792
2010-07-07 16:48:16 +00:00
ffe64b1ee5
Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
...
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.
llvm-svn: 107791
2010-07-07 16:47:08 +00:00
87fb4e8fcd
Simplify FastISel's constructor by giving it a FunctionLoweringInfo
...
instance, rather than pointers to all of FunctionLoweringInfo's
members.
This eliminates an NDEBUG ABI sensitivity.
llvm-svn: 107789
2010-07-07 16:29:44 +00:00
e784616fbb
Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This will
...
allow target-specific fast-isel code to make use of it directly.
llvm-svn: 107787
2010-07-07 16:01:37 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
...
code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
ca97c92eb4
add some triple for minix, patch by Kees van Reeuwijk from PR7582
...
llvm-svn: 107785
2010-07-07 15:52:27 +00:00
c54936c109
Move ArgFlagsTy, OutputArg, and InputArg out of SelectionDAGNodes.h and
...
into a new header, TargetCallingConv.h.
llvm-svn: 107782
2010-07-07 15:28:42 +00:00
498e5f899d
Move CallingConvLower.cpp out of the SelectionDAG directory.
...
llvm-svn: 107781
2010-07-07 15:15:27 +00:00
8e1338eea8
Fix more places assuming subregisters have live intervals
...
llvm-svn: 107780
2010-07-07 14:41:22 +00:00
4e39130919
adapt condition for changed default build mode
...
who knows how to cover Asserts or Debug separately
please do not hesitate to extend this
llvm-svn: 107779
2010-07-07 14:37:04 +00:00
88c547ede9
Add a getFirstNonPHI utility function.
...
llvm-svn: 107778
2010-07-07 14:33:51 +00:00
5b0a8a863f
Minore code simplification.
...
llvm-svn: 107777
2010-07-07 14:30:04 +00:00
00ef93258a
Remove interprocedural-basic-aa and associated code. The AliasAnalysis
...
interface needs implementations to be consistent, so any code which
wants to support different semantics must use a different interface.
It's not currently worthwhile to add a new interface for this new
concept.
Document that AliasAnalysis doesn't support cross-function queries.
llvm-svn: 107776
2010-07-07 14:27:09 +00:00
f6a2a5a0ae
typo in comment, regeneration not necessary
...
llvm-svn: 107774
2010-07-07 13:58:46 +00:00
a22e8148d4
conditionalize by CallInst::ArgOffset
...
llvm-svn: 107767
2010-07-07 10:34:03 +00:00
90e80efe6b
conditionalize on CallInst::ArgOffset
...
llvm-svn: 107766
2010-07-07 09:43:45 +00:00
99ed90a7a0
minor cosmetic changes that happened to sit in my tree
...
llvm-svn: 107764
2010-07-07 09:29:07 +00:00
408bb192de
Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"
...
builds to "Release". The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts. The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown). This will bring them
in line with MacOS releases, which ship with assertions disabled. It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.
llvm-svn: 107758
2010-07-07 07:48:00 +00:00
6d122aef97
Add AVX SSE4.2 instructions
...
llvm-svn: 107752
2010-07-07 03:39:29 +00:00
3df55b2d6f
Use only one multiclass to pinsrq instructions
...
llvm-svn: 107750
2010-07-07 01:43:01 +00:00
fd6c808154
Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes
...
llvm-svn: 107749
2010-07-07 01:33:38 +00:00
8f5472a8e8
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
...
llvm-svn: 107747
2010-07-07 01:14:56 +00:00
6430c7350d
Add AVX SSE4.1 extractps and pinsr instructions
...
llvm-svn: 107746
2010-07-07 01:01:13 +00:00
f0e551d4f4
Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.
...
Buildbot breakage.
llvm-svn: 107744
2010-07-07 00:32:25 +00:00
5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
...
llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3198483851
Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
...
they've been tested to work.
llvm-svn: 107742
2010-07-07 00:07:57 +00:00
f3116ebe96
Add AVX SSE4.1 Extract Integer instructions
...
llvm-svn: 107740
2010-07-07 00:07:24 +00:00
dc0a0659be
By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
...
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.
llvm-svn: 107734
2010-07-06 23:44:52 +00:00
e2d3067f6b
Remove references to INSERT_SUBREG after de-SSA
...
llvm-svn: 107732
2010-07-06 23:40:35 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
...
allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
ce65663330
Accept RIP-relative symbols with 'i' constraint, and
...
print the (%rip) only if the 'a' modifier is present.
PR 7528.
llvm-svn: 107727
2010-07-06 23:27:00 +00:00
70ee3ecd33
Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
...
INSERT_SUBREG will now only appear in SSA machine instructions.
Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.
llvm-svn: 107726
2010-07-06 23:26:25 +00:00
48deb12593
Track defs for all aliases in NEONMoveFix.
...
This means that an instruction defining an S register will affect the domain of
the parent D register.
llvm-svn: 107725
2010-07-06 23:26:23 +00:00
1f9ad516c6
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107723
2010-07-06 23:15:17 +00:00
6f01541ae6
Make test not hang waiting for input.
...
llvm-svn: 107721
2010-07-06 23:06:58 +00:00
35702d27c4
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
...
llvm-svn: 107720
2010-07-06 23:01:41 +00:00
13f0260e76
Fix comment from previous patch
...
llvm-svn: 107717
2010-07-06 22:38:32 +00:00
e2bd058d32
Add AVX vblendvpd, vblendvps and vpblendvb instructions
...
Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
ee0cb70381
CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
...
SelectBasicBlock doesn't needs its BasicBlock argument.
llvm-svn: 107712
2010-07-06 22:19:37 +00:00
a3ca21b228
Propagate debug loc.
...
llvm-svn: 107710
2010-07-06 22:08:15 +00:00
4c1ca29039
Represent NEON load/store alignments in bytes, not bits.
...
llvm-svn: 107701
2010-07-06 21:26:18 +00:00
15fed3bd30
One more case assuming that subregs have live ranges.
...
llvm-svn: 107700
2010-07-06 21:13:03 +00:00
72ed8908ee
Closing tags start with slashes.
...
llvm-svn: 107699
2010-07-06 21:07:14 +00:00
bcf3409107
Fix buildbot breakage where a def is missing.
...
llvm-svn: 107698
2010-07-06 21:06:39 +00:00
b36df17b08
Add fixme.
...
llvm-svn: 107697
2010-07-06 21:05:17 +00:00
5eff9ca26e
minor typo
...
llvm-svn: 107696
2010-07-06 20:51:35 +00:00
a64c0a3d22
Be more forgiving when calculating alias interference for physreg coalescing.
...
It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.
This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.
llvm-svn: 107695
2010-07-06 20:31:51 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
...
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
e3ecf358d0
Add X86_64 ELF relocation values and ELF64 relocation classes.
...
Patch from Roman Divacky.
llvm-svn: 107688
2010-07-06 18:44:02 +00:00
13d85ea43c
Add some more ELF OSABI values as found in the System V Application
...
Binary Interface specification.
llvm-svn: 107685
2010-07-06 18:36:57 +00:00
dfc8b745a2
Fix to 80-col.
...
llvm-svn: 107684
2010-07-06 18:35:20 +00:00
3caf24d557
Provide IRBuilder conveniences for creating integer constants at common widths,
...
and give a more precise return type for some of the type-creation methods.
llvm-svn: 107683
2010-07-06 18:34:49 +00:00
14b58dac8d
Alphabetize the list of function parameters.
...
llvm-svn: 107680
2010-07-06 18:24:09 +00:00
23a7593534
Fix PR7545 crash.
...
llvm-svn: 107678
2010-07-06 18:18:32 +00:00
e9512f0a25
Provide an abstraction to save and restore the current insertion point of
...
an IRBuilder.
llvm-svn: 107677
2010-07-06 18:07:52 +00:00
7c510aa7bc
Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
...
if profitable.
llvm-svn: 107673
2010-07-06 16:24:34 +00:00
dde2ba0b60
tighten up this code.
...
llvm-svn: 107670
2010-07-06 15:59:27 +00:00
83cec97479
Bring the list of passes and their descriptions up to date.
...
Patch by Kenneth Hoste.
llvm-svn: 107669
2010-07-06 15:52:15 +00:00
f4f04107ef
Revert r107655.
...
llvm-svn: 107668
2010-07-06 15:49:48 +00:00
33134fa75f
second round of low-level interface squeeze-out:
...
making all of CallInst's low-level operand accessors
private
If you get compile errors I strongly urge you to
update your code.
I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.
You have several options to update your code:
- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
low-level accessors if your code is definitely
operand-order agnostic.
If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):
<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271 >
llvm-svn: 107667
2010-07-06 15:44:11 +00:00
4e49b59dad
Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands
...
which do not depend on SelectionDAG.
llvm-svn: 107666
2010-07-06 15:39:54 +00:00
a96f12ee7c
Add a new CCValAssign LocInfo value, and a comment explaining what it
...
should be used for.
llvm-svn: 107661
2010-07-06 15:35:06 +00:00
2b2a1c3c86
Make getMinimalPhysRegClass' comment mention what makes it different
...
from getPhysicalRegisterRegClass.
llvm-svn: 107660
2010-07-06 15:31:55 +00:00
6c858db40c
Note the relationship between C99 restrict and LLVM noalias, and
...
clarify a few other things.
llvm-svn: 107659
2010-07-06 15:26:33 +00:00
e415230477
Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards.
...
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').
llvm-svn: 107658
2010-07-06 15:24:56 +00:00
1e33b18e28
Add some more TODO comments.
...
llvm-svn: 107657
2010-07-06 15:23:00 +00:00
f855b39edd
Add a comment.
...
llvm-svn: 107656
2010-07-06 15:21:57 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
...
the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
8f06b4a294
Remove mistakenly added test.
...
llvm-svn: 107641
2010-07-06 05:20:13 +00:00
2ad0c779c3
Fix up -fstack-protector on linux to use the segment
...
registers. Split out testcases per architecture and os
now.
Patch from Nelson Elhage.
llvm-svn: 107640
2010-07-06 05:18:56 +00:00
dace239949
Detabify this file.
...
llvm-svn: 107637
2010-07-06 03:53:43 +00:00
aef27695e7
Add default value to setIsNoInline for parity with the other methods of its
...
kind.
Also fold some functions that fit on a line to a single line.
llvm-svn: 107636
2010-07-06 03:53:22 +00:00
19a10a599d
Fix typo 'getter' where 'setter' was intended.
...
llvm-svn: 107635
2010-07-06 03:52:37 +00:00
d429846eca
Have the X86 backend use Triple instead of a string and some enums.
...
llvm-svn: 107625
2010-07-05 19:26:33 +00:00
d5ac287140
Remove some unused/redundant code.
...
llvm-svn: 107622
2010-07-05 18:40:09 +00:00
c4a7073db3
more tidying.
...
llvm-svn: 107615
2010-07-05 05:53:14 +00:00
60db4557cd
another v2f32 case, in this case showing poor codegen.
...
llvm-svn: 107614
2010-07-05 05:52:56 +00:00
7b909ac785
some notes about suboptimal insertps's
...
llvm-svn: 107613
2010-07-05 05:48:41 +00:00
2c0315a0f3
random tidying
...
llvm-svn: 107612
2010-07-05 05:36:21 +00:00
6d60a14251
rip out even more sporadic v2f32 support.
...
llvm-svn: 107610
2010-07-05 04:38:33 +00:00
feb2467bf4
rip out the various v2f32 "mmx" handling logic, now that
...
v2f32 is illegal on x86.
llvm-svn: 107609
2010-07-05 04:36:27 +00:00
431e81f2fb
fix test on non-x86 hosts.
...
llvm-svn: 107608
2010-07-05 03:56:55 +00:00
ac0a210789
Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.
...
llvm-svn: 107602
2010-07-04 23:24:23 +00:00
45cc4d74a3
Just rip v2f32 support completely out of the X86 backend. In
...
the example in the testcase, we now generate:
_test1: ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret
instead of:
_test1: ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret
v2f32 support did not work reliably because most of the X86
backend didn't know it was legal. It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode. If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32. However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.
llvm-svn: 107601
2010-07-04 23:07:25 +00:00
681b926d54
fix PR7518 - terrible codegen of <2 x float>, by only marking
...
v2f32 as legal in 32-bit mode. It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.
llvm-svn: 107600
2010-07-04 22:57:10 +00:00
cb948d3329
indentation
...
llvm-svn: 107599
2010-07-04 22:56:10 +00:00
f3aeb2c22c
Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.
...
llvm-svn: 107591
2010-07-04 18:52:05 +00:00
30f33eb935
indmemrem and lowerallocs are gone.
...
llvm-svn: 107587
2010-07-04 17:36:43 +00:00
199cacf179
Revert r107583. I no longer think that this is the way to solve the problem.
...
llvm-svn: 107585
2010-07-04 09:16:57 +00:00
701aa053b9
Mark sse_load_f32 and sse_load_f64 as having memory operands
...
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.
llvm-svn: 107583
2010-07-04 08:59:55 +00:00
4cb5ce113e
back out r107580, I have seen what I wanted
...
llvm-svn: 107582
2010-07-04 08:59:25 +00:00
f844642350
Proper indentation.
...
llvm-svn: 107581
2010-07-04 08:58:43 +00:00
3c1f66b0eb
[another test commit, just to tickle the selfhost buildbots; I'll back out in a few minutes]
...
second round of low-level interface squeeze-out:
making all of CallInst's low-level operand accessors
private
If you get compile errors I strongly urge you to
update your code.
I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.
You have several options to update your code:
- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
low-level accessors if your code is definitely
operand-order agnostic.
If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):
<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271 >
llvm-svn: 107580
2010-07-04 07:42:31 +00:00
c8f595212f
Minor amendment to switch-lowering improvement.
...
llvm-svn: 107569
2010-07-03 08:43:32 +00:00
836fdbc85b
Note switch-lowering inefficiency.
...
llvm-svn: 107565
2010-07-03 07:38:12 +00:00
ca99012ac0
Add AVX SSE4.1 blend, mpsadbw and vdp
...
llvm-svn: 107560
2010-07-03 01:37:03 +00:00
bc75502f09
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
...
llvm-svn: 107558
2010-07-03 01:15:47 +00:00
Dan Gohman