b1a1512119
start using the new helper methods a bit.
...
llvm-svn: 135251
2011-07-15 06:08:15 +00:00
ac5fb56682
add CFP::isNegative() and ConstnatInt::isNegative() methods.
...
Devirtualize the isNegativeZeroValue method.
llvm-svn: 135249
2011-07-15 05:58:04 +00:00
07bd69c446
bump pointer allocate LLVM IR types, since they are never deallocated.
...
llvm-svn: 135248
2011-07-15 05:49:15 +00:00
e983082bdb
remove the InvalidateStructLayoutInfo API, which is dead and unnecessary now
...
that type refinement is toast.
llvm-svn: 135245
2011-07-15 05:21:59 +00:00
65667dbf2d
Remove an unnecessary header from this file. I don't think this header
...
was really intended, and it may have been required prior to some of the
recent refactors. Including it however causes LLVMX86Desc to need
symbols from LLVMX86CodeGen, forming a dependency cycle. This was masked
in almost all builds: Clang, and GCC w/ optimizations didn't actually
emit the symbols!
llvm-svn: 135242
2011-07-15 04:16:38 +00:00
124342c467
The *MCAsmInfo.cpp files use ADT/Triple code, so add the Support dep.
...
llvm-svn: 135239
2011-07-15 02:34:03 +00:00
a83b37a9db
Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
...
solution but it is a small step towards removing the horror that is
TargetAsmInfo.
llvm-svn: 135237
2011-07-15 02:09:41 +00:00
9b8605f787
Remove setting the bit for personality function. It should be set by the linker.
...
llvm-svn: 135236
2011-07-15 01:42:32 +00:00
9a0001aedb
Major update to CMake build to reflect changes in r135219 in the
...
backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.
Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.
llvm-svn: 135234
2011-07-15 00:40:52 +00:00
445d39b0b7
Add new configure option, --with-bug-report-url, which allows users/vendors to
...
specify where bug reports should be submitted.
Part of rdar://9575623
llvm-svn: 135233
2011-07-15 00:37:26 +00:00
001c4f3ff0
Do not get confused by multiple empty lexical scopes inlined at one location.
...
llvm-svn: 135232
2011-07-15 00:30:39 +00:00
c41d4fe243
Output MachO section names in the form SEGMENT,section.
...
llvm-svn: 135231
2011-07-15 00:29:02 +00:00
56498d167a
Add support for 64 bit objects to MachOObjectFile.
...
- I don't see a better way than duplicating all the code.
llvm-svn: 135229
2011-07-15 00:14:48 +00:00
b1d80722a8
MachOObjectFile: Change isSectionText to return true for sections named text, not for load commands name __TEXT (which isn't the case in actual object files)
...
llvm-svn: 135228
2011-07-15 00:14:46 +00:00
c998f71d14
Encode that we have a personality function.
...
llvm-svn: 135227
2011-07-15 00:07:31 +00:00
1705ab00ab
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
...
llvm-svn: 135219
2011-07-14 23:50:31 +00:00
82432f7edf
CMake: Add a new configuration option LLVM_BUILD_CLANG that's
...
available when Clang is found within the LLVM tree. If enabled (the
default), Clang will be built as part of LLVM. If disabled, Clang will
be skipped... and can be built by configuring a separate object
directory just for Clang. This helps break up the monolithic
LLVM+Clang project that many Clang developers use, improving
build/load times.
llvm-svn: 135218
2011-07-14 23:49:55 +00:00
dafd598f05
* If we have an LSDA, we need to mark it in the encoding.
...
* The personality function should be encoded as an absolute pointer to the function.
llvm-svn: 135215
2011-07-14 23:34:45 +00:00
4771159f9f
Refactor.
...
llvm-svn: 135212
2011-07-14 23:17:49 +00:00
19ed0829a3
cmake/modules/LLVMLibDeps.cmake: Update since r135184.
...
llvm-svn: 135211
2011-07-14 23:12:02 +00:00
1f9913fdb2
Eliminate redundant LLVMContext argument.
...
Improve DbgScope->dump() output.
llvm-svn: 135207
2011-07-14 22:30:56 +00:00
cbd3bb27d7
Undo r135191 (i.e. reapply Chris's patch. Now linker maps NamedMDNodes first, so there is not any need to map DebugLoc).
...
llvm-svn: 135205
2011-07-14 22:14:06 +00:00
d2d49862fc
Link NamedMDNode before linking function bodies.
...
llvm-svn: 135204
2011-07-14 22:13:07 +00:00
03a8a16f32
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
...
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
llvm-svn: 135203
2011-07-14 22:04:21 +00:00
2d825b5ecf
* Redo the permutation encoding for frameless stacks to be more like what the
...
unwind library expects.
* Comment the permutation encoding for frameless stacks.
llvm-svn: 135202
2011-07-14 22:01:34 +00:00
4db3844e8b
Add dump()
...
llvm-svn: 135200
2011-07-14 21:50:04 +00:00
3ceac21d37
Add OperandTypes for Thumb branch targets.
...
llvm-svn: 135199
2011-07-14 21:47:24 +00:00
9654eef493
Port operand types for ARM and X86 over from EDIS to the .td files.
...
llvm-svn: 135198
2011-07-14 21:47:22 +00:00
c8dc46bc01
Add a new field to MCOperandInfo that contains information about the type of the Operand.
...
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.
llvm-svn: 135197
2011-07-14 21:47:18 +00:00
51849920f1
Add some testcases for ARM MLA/MLS instructions.
...
llvm-svn: 135196
2011-07-14 21:43:05 +00:00
26e7449443
ARM MCRR/MCRR2 immediate operand range checking.
...
llvm-svn: 135192
2011-07-14 21:26:42 +00:00
fb9f4926d1
revert r135172 until Devang and I figure out the right answer.
...
llvm-svn: 135191
2011-07-14 21:25:42 +00:00
d37d2025e9
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
f470b5b49a
After type-system-rewrite branch update the Cpp backend to not use OpaqueType.
...
llvm-svn: 135186
2011-07-14 21:04:35 +00:00
e336a290a6
Enable some tests we now handle correctly.
...
llvm-svn: 135185
2011-07-14 21:02:23 +00:00
bc153d49b7
Next round of MC refactoring. This patch factor MC table instantiations, MC
...
registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
2011-07-14 20:59:42 +00:00
0c134b52b9
simplify this logic now that GlobalAlias::isDeclaration is fixed.
...
llvm-svn: 135183
2011-07-14 20:23:05 +00:00
81210d232d
Fix GlobalValue::isDeclaration() to always consider aliases to be definitions.
...
llvm-svn: 135182
2011-07-14 20:22:18 +00:00
92464be28c
Check register class matching instead of width of type matching
...
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.
Fixes PR10352 and rdar://9777108
llvm-svn: 135180
2011-07-14 20:13:52 +00:00
fa18793934
Reorganize ARM assembler aliases.
...
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.
llvm-svn: 135179
2011-07-14 19:47:47 +00:00
784ad24bad
Add LLVMConstNamedStruct to the C api to let its users create constants
...
of named struct types.
llvm-svn: 135178
2011-07-14 19:09:08 +00:00
4cc3bcd575
DebugLoc's don't hide any interesting types for TypeFinder to find.
...
llvm-svn: 135174
2011-07-14 18:58:40 +00:00
8f29491ffd
manually copy debugloc over to a new instruction in clone() instead
...
of calling getAllMetadata(). This is semantically identical, but doing
it this way avoids unpacking the DebugLoc.
llvm-svn: 135173
2011-07-14 18:57:51 +00:00
69eea72779
Stop the ValueMapper from calling getAllMetadata, which unpacks DebugLoc into
...
an MDNode. This saves a bunch of time and memory in the IR linker, e.g. when
doing LTO of files with debug info.
llvm-svn: 135172
2011-07-14 18:53:50 +00:00
6778597deb
Add 256-bit load/store recognition and matching in several places.
...
llvm-svn: 135171
2011-07-14 18:50:58 +00:00
1757e7abeb
Don't leak operands when putting them into a shift.
...
llvm-svn: 135169
2011-07-14 18:41:22 +00:00
2f9aeeef3b
Update ARM Assembly of LDM/STM.
...
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
llvm-svn: 135168
2011-07-14 18:35:38 +00:00
7c37b1cf51
The key of a StringMap can contain nul's in it, so having first() return
...
const char* doesn't make sense. Have it return StringRef instead.
llvm-svn: 135167
2011-07-14 18:31:43 +00:00
4f8dd9de31
though it isn't the case here, the key of a StringMap can
...
conceptually have nuls in it.
llvm-svn: 135165
2011-07-14 18:21:58 +00:00
8561721bce
add comments.
...
llvm-svn: 135164
2011-07-14 18:12:44 +00:00
923053a1d6
consolidate GlobalValue::isDeclaration into one
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non-virtual function.
llvm-svn: 135163
2011-07-14 18:10:41 +00:00
d616cf3497
ARM ISB assembly parsing tests.
...
llvm-svn: 135158
2011-07-14 18:02:25 +00:00
79617815c8
code cleanup
...
llvm-svn: 135157
2011-07-14 18:01:49 +00:00
b218202586
ARM ISB instruction assembly parsing.
...
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
llvm-svn: 135156
2011-07-14 18:00:31 +00:00
e6e1933f31
Change Intrinsic::getDeclaration and friends to take an ArrayRef.
...
llvm-svn: 135154
2011-07-14 17:45:39 +00:00
17cf05b953
add a couple more missing C api, patch by Vitaly Lugovskiy!
...
llvm-svn: 135151
2011-07-14 16:20:28 +00:00
34c8b08201
Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUE
...
instructions.
llvm-svn: 135146
2011-07-14 14:03:48 +00:00
78ee70bbe7
Simplify some functions in the C API by using an ArrayRef to directly reference the array passed to them instead of copying it to a std::vector.
...
llvm-svn: 135145
2011-07-14 11:44:09 +00:00
771f29677f
[VECTOR-SELECT]
...
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.
llvm-svn: 135144
2011-07-14 11:11:14 +00:00
db213c0400
Add assertion for the chain value type
...
llvm-svn: 135143
2011-07-14 10:37:54 +00:00
e03f15ad2b
Mention all API changes I've made since 2.9 was branched.
...
llvm-svn: 135142
2011-07-14 09:19:05 +00:00
0c666b4664
Add a testcase for r135123.
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Part of rdar://9761830
llvm-svn: 135133
2011-07-14 06:23:09 +00:00
e71ccde249
add C api for hte new type system rewrite API. Patch by Vitaly Lugovskiy!
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llvm-svn: 135132
2011-07-14 05:53:17 +00:00
c7ac690ba2
Unfortunately several files in MC are badly violating layering rule by using
...
TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.
This patch is but one small step towards fixing this. 500 more steps to go. :-(
llvm-svn: 135131
2011-07-14 05:43:07 +00:00
a153ca5885
Reapply r135121 with a fixed copy constructor.
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Original commit message:
Count references to interference cache entries.
Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.
This makes it possible to have multiple live cursors examining
interference for different physregs.
The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().
Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.
llvm-svn: 135130
2011-07-14 05:35:11 +00:00
d5234bbced
Simplify.
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llvm-svn: 135127
2011-07-14 01:52:45 +00:00
15cd5a3f12
Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient.
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llvm-svn: 135126
2011-07-14 01:38:42 +00:00
07d61edc30
Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as much as possible.
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llvm-svn: 135124
2011-07-14 01:14:57 +00:00
d6300d2956
Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-A
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Fixes rdar://9761830
llvm-svn: 135123
2011-07-14 01:12:15 +00:00
1d4badae74
Revert r135121 which broke a gcc-4.2 builder.
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llvm-svn: 135122
2011-07-14 00:58:38 +00:00
c270cb6e94
Count references to interference cache entries.
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Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.
This makes it possible to have multiple live cursors examining
interference for different physregs.
The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().
Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.
llvm-svn: 135121
2011-07-14 00:31:14 +00:00
bc2ae1c865
Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate.
...
llvm-svn: 135120
2011-07-14 00:22:31 +00:00
e6f8b1fac6
ARM tests for EOR instruction parsing and encoding.
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llvm-svn: 135119
2011-07-14 00:22:21 +00:00
e07ebe32bf
Simplify. Compile unit check inside hasValidLocation() did not add any value.
...
llvm-svn: 135118
2011-07-14 00:20:24 +00:00
f34e35da1c
Remove duplicate tests.
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llvm-svn: 135117
2011-07-14 00:19:19 +00:00
a0958d7abf
ARM Assembler support for DSB instruction.
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Add instalias for default 'sy' option. Add tests.
llvm-svn: 135116
2011-07-14 00:18:13 +00:00
d7e9937175
Reapply r135074 and r135080 with a fix.
...
The cache entry referenced by the best split candidate could become
clobbered by an unsuccessful candidate.
The correct fix here is to use reference counts on the cache entries.
Coming up.
llvm-svn: 135113
2011-07-14 00:17:10 +00:00
56a20a492b
DMB instalias needs the same predicate as the instruction.
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llvm-svn: 135112
2011-07-14 00:10:26 +00:00
a9195bcff0
Fix typo in DEBUG message.
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llvm-svn: 135111
2011-07-14 00:04:53 +00:00
2cce0d103d
Add DEBUG messages.
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llvm-svn: 135110
2011-07-14 00:03:58 +00:00
44c3f08e85
ARM Assembler support for DMB instruction.
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Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
llvm-svn: 135109
2011-07-13 23:40:38 +00:00
199b683a6e
Update comments. These are for assembler, too.
...
llvm-svn: 135107
2011-07-13 23:33:10 +00:00
651b230ca0
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
...
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
d11ea81db0
Add code to handle a "frameless" unwind stack.
...
The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".
llvm-svn: 135103
2011-07-13 23:03:31 +00:00
507ba77465
ARM Assembler support for DBG instruction.
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Add range checking and testing for parsing and encoding of DBG instruction.
llvm-svn: 135102
2011-07-13 22:59:38 +00:00
3c4d652210
We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.
...
llvm-svn: 135099
2011-07-13 22:28:55 +00:00
307de01867
ARM parsing and encoding tests for CMN/CMP.
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llvm-svn: 135098
2011-07-13 22:26:58 +00:00
9908c17666
struct Init -> class Init
...
Rename struct Init to class Init for consistency and in preparation
for making Init a FoldingSetNode.
llvm-svn: 135097
2011-07-13 22:25:51 +00:00
fae30b240b
Revert r135074 and r135080. They broke clamscan.
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llvm-svn: 135096
2011-07-13 22:20:09 +00:00
9559d360e5
Shuffle ARM assembly tests a bit.
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llvm-svn: 135095
2011-07-13 22:19:10 +00:00
c5b4019a0d
Revert 135093. Think-o.
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llvm-svn: 135094
2011-07-13 22:06:11 +00:00
ccc207773d
Correct range for thumb co-processor immediate
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llvm-svn: 135093
2011-07-13 22:03:11 +00:00
31756c2283
Range checking for CDP[2] immediates.
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llvm-svn: 135092
2011-07-13 22:01:08 +00:00
9613b64916
Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
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general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.
llvm-svn: 135088
2011-07-13 21:36:51 +00:00
7ba479d22f
The target specific node PANDN name is misleading. That happens because
...
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.
llvm-svn: 135087
2011-07-13 21:36:47 +00:00
ca7150b54d
Cleanup Thumb co-processor instructions a bit.
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Combine redundant base classes and such. No indended functional change.
llvm-svn: 135085
2011-07-13 21:35:10 +00:00
344ec79715
Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
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<rdar://problem/9763308>
llvm-svn: 135084
2011-07-13 21:29:53 +00:00
cabb48d511
Parameterize away the ARM T1Cop class.
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llvm-svn: 135082
2011-07-13 21:17:59 +00:00
adb29b6dbb
Fix predicates for Thumb co-processor instructions.
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They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
llvm-svn: 135081
2011-07-13 21:14:23 +00:00
5fba5b8eb9
Only keep the global split candidates that work out.
...
Some pysical registers create split solutions that would spill anywhere.
They should not even be considered in future multi-way global splits.
This does not affect code generation (yet).
llvm-svn: 135080
2011-07-13 20:49:46 +00:00
Chris Lattner