2338f6c57e
Add generic expansion of SUB when ADD and XOR
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are legal. Based on a patch by Micah Villmow.
llvm-svn: 71078
2009-05-06 11:29:50 +00:00
ab68cf24bb
Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.
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llvm-svn: 71057
2009-05-06 02:36:21 +00:00
bb2f10759e
If a MachineBasicBlock has multiple ways of reaching another block,
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allow it to have multiple CFG edges to that block. This is needed
to allow MachineBasicBlock::isOnlyReachableByFallthrough to work
correctly. This fixes PR4126.
llvm-svn: 71018
2009-05-05 21:10:19 +00:00
9bf9002161
Enable stack coloring with regs at -O3.
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llvm-svn: 71010
2009-05-05 20:30:36 +00:00
929b644b0f
Do not require variable debug info nodes to have a compile unit.
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For implicit decls like "self" and "_cmd" in ObjC, these decls
should not have a location.
llvm-svn: 70964
2009-05-05 04:55:56 +00:00
6fc03634db
Do not substitute if the new register isn't in the register class of the operand being updated.
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llvm-svn: 70953
2009-05-05 00:46:16 +00:00
1ff2727c95
Move getInstrOperandRegClass from the scheduler to TargetInstrInfo.
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llvm-svn: 70950
2009-05-05 00:30:09 +00:00
dbfb102523
Do forward and backward substitution to eliminate loads and stores when possible.
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llvm-svn: 70937
2009-05-04 23:13:13 +00:00
354b12259f
Make DBG_STOPPOINT nodes, and therefore DBG_LABEL labels, get a DebugLoc, so that it
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shows up in -print-machineinstrs. This doesn't appear to affect anything, but it was
weird for some DBG_LABELs to have DebugLocs but not all of them.
llvm-svn: 70921
2009-05-04 22:10:05 +00:00
71fb950b73
Restore a comment.
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llvm-svn: 70900
2009-05-04 19:23:45 +00:00
9ae29b2d8f
-Remove the DwarfWriter::RecordSourceLine calls from the instruction selectors.
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-Depend on DebugLocs for source line info.
(Comes with Regression-Be-Gone(tm))
llvm-svn: 70871
2009-05-04 16:23:49 +00:00
3f77805642
Make sure to color with only allocatable registers for the specific register class.
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llvm-svn: 70821
2009-05-04 03:30:11 +00:00
4b6072bcb8
The stack slots which share the same stack slot after coloring can, but do not have to, use the same register. In fact, they each may have different register class requirements.
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llvm-svn: 70815
2009-05-04 00:24:50 +00:00
79be34012f
Revert r70803 for now, it causes a regression.
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llvm-svn: 70811
2009-05-03 23:27:19 +00:00
ce7196b903
-Remove the DwarfWriter::RecordSourceLine calls from the instruction selectors.
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-Depend on DebugLocs for source line info.
llvm-svn: 70803
2009-05-03 22:03:35 +00:00
1de5cf548e
Typo.
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llvm-svn: 70792
2009-05-03 19:10:11 +00:00
210fc62a91
In some rare cases, the register allocator can spill registers but end up not utilizing registers at all. The fundamental problem is linearscan's backtracking can end up freeing more than one allocated registers. However, reloads and restores might be folded into uses / defs and freed registers might not be used at all.
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VirtRegMap keeps track of allocations so it knows what's not used. As a horrible hack, the stack coloring can color spill slots with *free* registers. That is, it replace reload and spills with copies from and to the free register. It unfold instructions that load and store the spill slot and replace them with register using variants.
Not yet enabled. This is part 1. More coming.
llvm-svn: 70787
2009-05-03 18:32:42 +00:00
2745bc92fa
Fix typo
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llvm-svn: 70770
2009-05-03 13:19:57 +00:00
05b7a7c8f8
Properly handle sdiv / udiv / srem / urem libcalls
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llvm-svn: 70764
2009-05-03 13:18:16 +00:00
399ad444fd
Proper name 16 bit libcalls
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llvm-svn: 70750
2009-05-03 13:14:08 +00:00
f3fc92d6fc
Add libcall expansion for 16 and 128 bit muls
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llvm-svn: 70749
2009-05-03 13:13:51 +00:00
97324cec99
-Move the DwarfWriter::ValidDebugInfo check to a static DIDescriptor::ValidDebugInfo
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-Create DebugLocs without the need to have a DwarfWriter around
llvm-svn: 70682
2009-05-03 08:50:41 +00:00
62a3124fb8
Allow CONCAT_VECTORS nodes to be legal or have custom lowering for some targets.
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Changes to take advantage of this will come later.
llvm-svn: 70560
2009-05-01 17:55:32 +00:00
80b9abf8f4
Simplify more code and add timer stuff.
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llvm-svn: 70539
2009-05-01 08:40:06 +00:00
03968bd796
Simplify more code.
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llvm-svn: 70537
2009-05-01 08:35:12 +00:00
87cbaf4bc9
Simplify some code.
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llvm-svn: 70534
2009-05-01 08:32:14 +00:00
1c24c74495
Fix whitespace. It was confusing me.
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llvm-svn: 70533
2009-05-01 08:25:13 +00:00
f8949a61bf
Code clean up. Bye bye PhysRegTracker.
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llvm-svn: 70524
2009-05-01 01:03:49 +00:00
a5037484a4
Make DebugLoc independent of DwarfWriter.
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-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)
llvm-svn: 70520
2009-04-30 23:22:31 +00:00
050631c0a6
Join cross class copies using getCommonSubClass()
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llvm-svn: 70513
2009-04-30 21:24:03 +00:00
007cbe91c5
Add a smarter heuristic to determine when to coalesce a virtual register with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead.
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This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping".
llvm-svn: 70503
2009-04-30 18:39:57 +00:00
fe0c648fee
Move helper functions for optimizing division by constant into the APInt
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class.
llvm-svn: 70488
2009-04-30 10:15:35 +00:00
5ab42e93c4
fix a regression handling indirect results: these need to be considered
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memory operands otherwise the writebacks get lost when the inline asm
doesn't otherwise have side effects. This fixes rdar://6839427, though
clang really shouldn't generate these anymore.
llvm-svn: 70455
2009-04-30 00:48:50 +00:00
026e5d7667
Instead of passing in an unsigned value for the optimization level, use an enum,
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which better identifies what the optimization is doing. And is more flexible for
future uses.
llvm-svn: 70440
2009-04-29 23:29:43 +00:00
7e6e352735
Fix infinite recursion in the C++ code which handles movddup by making it unnecessary.
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llvm-svn: 70425
2009-04-29 22:47:44 +00:00
1971dc7007
MachineInstr::isRegTiedTo{Use,Def}Operand can safely be made const.
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llvm-svn: 70408
2009-04-29 20:57:16 +00:00
39b59db245
Update comment, replace theoretically impossible check with an assert.
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llvm-svn: 70391
2009-04-29 18:13:31 +00:00
9cce299cc8
spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them.
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llvm-svn: 70378
2009-04-29 07:16:34 +00:00
5f829d896d
Implement review feedback for vector shuffle work.
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llvm-svn: 70372
2009-04-29 05:20:52 +00:00
ccd30945f9
Add a public method called getAddressSpace() to the GlobalAddressSDNode.
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llvm-svn: 70366
2009-04-29 04:43:24 +00:00
7d10386113
Disable the load-shrinking optimization from looking at
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anything larger than 64-bits, avoiding a crash. This should
really be fixed to use APInts, though type legalization happens
to help us out and we get good code on the attached testcase at
least.
This fixes rdar://6836460
llvm-svn: 70360
2009-04-29 03:45:07 +00:00
cfb4cae201
Determine allocation 'preference' with right register class. I haven't seen this changing codegen so no test case.
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llvm-svn: 70351
2009-04-29 00:42:27 +00:00
084669a1c9
Second attempt:
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Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.
Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.
llvm-svn: 70343
2009-04-29 00:15:41 +00:00
e0eb5483d1
Move getMatchingSuperReg() out of coalescer and into TargetRegisterInfo.
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llvm-svn: 70309
2009-04-28 18:29:27 +00:00
fb9e23b217
Don't coalesce a physical register with an incompatible virtual register.
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If the physical register does not belong to the virtual register's regclass,
don't coalesce. The physical register could be an invalid operand for an
instruction using the vreg.
The regclass matching is done after determining the actual subregisters being copied.
llvm-svn: 70298
2009-04-28 16:34:35 +00:00
99b1b27dc2
Initialized arrays can be in any address space.
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llvm-svn: 70297
2009-04-28 16:34:20 +00:00
604248e81f
Move getSubRegisterRegClass from ScheduleDagSDNodesEmit.cpp to a TargetRegisterClass method.
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Also make the method non-asserting. It will return NULL when given an invalid subreg index.
The method is needed by an upcoming patch.
llvm-svn: 70296
2009-04-28 16:34:09 +00:00
7e09994cb8
Fix PR4034. Bug in LiveInterval::join when it's compacting new valno's.
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llvm-svn: 70291
2009-04-28 06:24:09 +00:00
c3884be983
Fix for PR4051. When 2address pass delete an instruction, update kill info when necessary.
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llvm-svn: 70279
2009-04-28 02:12:36 +00:00
56f2987a87
r70270 isn't ready yet. Back this out. Sorry for the noise.
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llvm-svn: 70275
2009-04-28 01:04:53 +00:00
Duncan Sands