78485ad65e
Thumb conditional branch binary encodings. rdar://8745367
...
llvm-svn: 121493
2010-12-10 17:13:40 +00:00
c92136ffb6
Fix the leak from r121401 of the Operands erased in the list but not deleted.
...
llvm-svn: 121450
2010-12-10 01:41:56 +00:00
0c4838bab7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
...
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
cb4d8f2e74
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
...
but it gets many more of them correct than it did previously.
llvm-svn: 121414
2010-12-09 21:34:47 +00:00
3ef19d9d48
Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
...
the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.
llvm-svn: 121408
2010-12-09 20:27:52 +00:00
68b27eb9d1
Rename CB/CBZ specific fixup accordingly.
...
llvm-svn: 121404
2010-12-09 19:50:12 +00:00
3164a346e6
Add support for parsing ARM arithmetic instructions that update or don't update
...
the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
llvm-svn: 121401
2010-12-09 19:19:43 +00:00
62b68112da
Rename the encoder method for t_cbtarget to match.
...
llvm-svn: 121399
2010-12-09 19:04:53 +00:00
529c7e8d1f
Thumb needs a few different encoding schemes for branch targets. Rename
...
t_brtarget to be more specific.
llvm-svn: 121398
2010-12-09 19:01:46 +00:00
5fccad84a3
ARM stm/ldm instructions require more than one register in the register list.
...
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460
llvm-svn: 121391
2010-12-09 18:31:13 +00:00
23f8671e05
tidy up.
...
llvm-svn: 121371
2010-12-09 16:15:41 +00:00
c0b669f5c0
80 columns.
...
llvm-svn: 121370
2010-12-09 16:14:46 +00:00
817b7cd7b8
Fix encoding of the immediate operands on post-indexed LDR and friends.
...
llvm-svn: 121354
2010-12-09 02:56:12 +00:00
2a2e65c452
Fix up some comments.
...
llvm-svn: 121351
2010-12-09 01:57:45 +00:00
3e6ee1db3e
Fix Thumb2 fixups for ldr.
...
llvm-svn: 121350
2010-12-09 01:51:07 +00:00
6233189713
Add a textual message to the assert.
...
llvm-svn: 121349
2010-12-09 01:23:51 +00:00
ed40288eb4
Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are
...
referencing the stack pointer as they say they are.
llvm-svn: 121347
2010-12-09 01:22:19 +00:00
bd30afe4c2
When using multiple instructions to reference a frame index, make sure to
...
update the opcode when necessary as well as the source register.
llvm-svn: 121346
2010-12-09 01:22:13 +00:00
0b2630c500
The add/sub SP instructions are really pseudos. The assembler should ignore
...
them.
llvm-svn: 121345
2010-12-09 01:21:27 +00:00
eb369f84ec
Remove unused variables
...
llvm-svn: 121343
2010-12-09 01:04:43 +00:00
14e41271b7
Fix typo in Thumb2 branch fixup.
...
llvm-svn: 121342
2010-12-09 01:02:09 +00:00
f75412dec7
Remove extraneous semicolon.
...
llvm-svn: 121338
2010-12-09 00:51:54 +00:00
c4d333f02a
Attempt to make the bit-twiddling readable resulted in the binary value being
...
overwritten.
llvm-svn: 121337
2010-12-09 00:44:33 +00:00
3392bfc8f3
The BLX instruction is encoded differently than the BL, because why not? In
...
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
302d5fd0d8
Fix Thumb2 BCC encoding and fixups.
...
llvm-svn: 121329
2010-12-09 00:27:41 +00:00
e296ee830a
Style nit and whitespace cleanup
...
llvm-svn: 121317
2010-12-08 23:35:25 +00:00
9672c9a793
Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME
...
for more thorough cleanup.
llvm-svn: 121315
2010-12-08 23:30:19 +00:00
a5c666654e
Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends.
...
llvm-svn: 121314
2010-12-08 23:24:29 +00:00
ba8b6d9a1c
Removed dead comment.
...
llvm-svn: 121313
2010-12-08 23:19:44 +00:00
c79c5f6e8c
ARM/MC/ELF TPsoft is now a proper pseudo inst.
...
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
llvm-svn: 121312
2010-12-08 23:14:44 +00:00
e829c674bb
T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead.
...
llvm-svn: 121311
2010-12-08 23:13:01 +00:00
fd0e4c0fe9
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434
...
llvm-svn: 121310
2010-12-08 23:12:09 +00:00
51937f9963
Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434
...
llvm-svn: 121309
2010-12-08 23:04:16 +00:00
a7d6aa902a
Support the "target" encodings for the CB[N]Z instructions.
...
llvm-svn: 121308
2010-12-08 23:01:43 +00:00
7f3e9150d0
Fix an obvious cut-n-paste error.
...
llvm-svn: 121307
2010-12-08 23:01:18 +00:00
663e4ce357
Add operand encoding for Thumb2 addw SP + imm. rdar://8745434
...
llvm-svn: 121305
2010-12-08 22:50:19 +00:00
47e3cc54f8
Parameterize opcode encoding bits for Thumb2 extended precision integer
...
multiply instructions.
llvm-svn: 121301
2010-12-08 22:38:41 +00:00
c3b0b10708
Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555
...
llvm-svn: 121297
2010-12-08 22:29:28 +00:00
572e56dfb2
Simplify T2 operand assignment notation a bit. No need to specify a bit range
...
for the source field when it's the whole thing that's being referenced.
llvm-svn: 121291
2010-12-08 22:10:43 +00:00
3c68561453
Tweak ARM fixup value adjustments for Thumb to better handle the half-word
...
ordering of thumb mode.
llvm-svn: 121280
2010-12-08 20:32:07 +00:00
00067fb147
Generalize PostRAHazardRecognizer so it can be used in any pass for
...
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.
llvm-svn: 121274
2010-12-08 20:04:29 +00:00
dae32fd206
Improve comment.
...
llvm-svn: 121272
2010-12-08 19:31:11 +00:00
d18f98b969
Add initializer.
...
llvm-svn: 121262
2010-12-08 15:36:45 +00:00
9d54ae6332
Add comments.
...
llvm-svn: 121238
2010-12-08 06:29:02 +00:00
8a6449c46e
Add support for loading from a constant pool.
...
llvm-svn: 121226
2010-12-08 01:57:09 +00:00
87055ed6f4
Let target asm backends see assembler flags as they go by. Use that to handle
...
thumb vs. arm mode differences in WriteNopData().
llvm-svn: 121219
2010-12-08 01:16:55 +00:00
72ce453c73
Simplify the byte reordering logic slightly.
...
llvm-svn: 121216
2010-12-08 00:21:33 +00:00
0f7142d808
VLDR fixups need special handling under Thumb. While the encoding is the same,
...
the order of the bytes in the data stream is flipped around.
llvm-svn: 121215
2010-12-08 00:18:36 +00:00
56de7c2773
Fix a warning about a variable which is only used in an assertion.
...
llvm-svn: 121206
2010-12-07 23:26:21 +00:00
f09c44c7ab
Cleanup in the Darwin end. No functionality change.
...
llvm-svn: 121198
2010-12-07 23:11:00 +00:00
775ead3293
Fix a bad prologue / epilogue codegen bug where the compiler would emit illegal
...
vpush instructions to save / restore VFP / NEON registers like this:
vpush {d8,d10,d11}
vpop {d8,d10,d11}
vpush and vpop do not allow gaps in the register list.
rdar://8728956
llvm-svn: 121197
2010-12-07 23:08:38 +00:00
721724e643
A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. No
...
functionality change.
llvm-svn: 121195
2010-12-07 23:05:20 +00:00
49bcd6ff85
Binary encoding for ARM tLDRspi and tSTRspi.
...
llvm-svn: 121186
2010-12-07 21:50:47 +00:00
cf096a431a
Fix Thumb2 encoding of the S bit.
...
llvm-svn: 121182
2010-12-07 20:50:15 +00:00
327cf8ee5f
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
...
possible. They were duplicates for everything exception the source pattern
before.
llvm-svn: 121179
2010-12-07 20:41:06 +00:00
de75ab9a09
Code clean up; no functionality change.
...
llvm-svn: 121176
2010-12-07 20:11:46 +00:00
c27c956966
Code clean up; no functionality change.
...
llvm-svn: 121172
2010-12-07 19:59:34 +00:00
6e517d658e
Encode the literal field for tCMPzi instruction.
...
llvm-svn: 121153
2010-12-07 17:48:24 +00:00
cfa9a893df
Add parens to pacify gcc.
...
llvm-svn: 121142
2010-12-07 15:50:35 +00:00
583abbc4df
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and
...
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.
llvm-svn: 121120
2010-12-07 08:25:19 +00:00
99ea8a3510
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
...
llvm-svn: 121082
2010-12-07 00:45:21 +00:00
9e1994698d
Add fixup for Thumb1 BL/BLX instructions.
...
llvm-svn: 121072
2010-12-06 23:57:07 +00:00
0f30fec0bd
Remove the instruction fragment to data fragment lowering since it was causing
...
freed data to be read. I will open a bug to track it being reenabled.
llvm-svn: 121028
2010-12-06 19:08:48 +00:00
c1ee8e35d2
Revert r121021, which broke the buildbots.
...
llvm-svn: 121026
2010-12-06 18:57:40 +00:00
67f13b19b5
Trailing whitespace.
...
llvm-svn: 121024
2010-12-06 18:47:44 +00:00
bb4a76fc95
Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
...
llvm-svn: 121021
2010-12-06 18:35:51 +00:00
968c927201
Encode the register operand of ARM CondCode operands correctly. ARM::CPSR if
...
the instruction is predicated, reg0 otherwise.
llvm-svn: 121020
2010-12-06 18:30:57 +00:00
0bfb4d5043
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
...
not an immediate. It stores either ARM::CPSR or reg0.
llvm-svn: 121018
2010-12-06 18:21:12 +00:00
abd6d2742a
Eliminate unneeded #include's.
...
llvm-svn: 120971
2010-12-05 23:41:43 +00:00
70fbbf534b
ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.
...
llvm-svn: 120966
2010-12-05 23:08:57 +00:00
12f4d615ab
Code clean up.
...
llvm-svn: 120965
2010-12-05 23:03:45 +00:00
b8a662f0d1
Remove an unused variable.
...
llvm-svn: 120964
2010-12-05 23:03:35 +00:00
62c7b5bf76
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
...
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
llvm-svn: 120960
2010-12-05 22:04:16 +00:00
ed854baad5
The Thumb tADDrSPi instruction is not valid when the destination is SP.
...
Check for that and try narrowing it to tADDspi instead. Radar 8724703.
llvm-svn: 120892
2010-12-04 04:40:19 +00:00
ce18d7ebb5
Encode condition code for Thumb1 conditional branch instruction.
...
llvm-svn: 120865
2010-12-04 00:20:40 +00:00
5bae054f07
Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.
...
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577
llvm-svn: 120858
2010-12-03 23:54:18 +00:00
127d7485f1
Use correct variable names to match the patterns.
...
llvm-svn: 120857
2010-12-03 23:44:24 +00:00
a09cbbeef5
Match pattern operand names to expected encoding field names. This corrects the
...
operand encoding ordering of the instruction.
llvm-svn: 120852
2010-12-03 23:21:25 +00:00
e4fee20498
Remove incorrect BL target encoding (it's similar to, but not the same as the
...
ARM instruction). Add encoding of bits 13 and 11.
llvm-svn: 120849
2010-12-03 22:33:42 +00:00
567ebd0cb5
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
...
halfword being emitted to the stream first. rdar://8728174
llvm-svn: 120848
2010-12-03 22:31:40 +00:00
ca7eaaafda
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
...
32-bit wide version by adding the .w suffix.
llvm-svn: 120838
2010-12-03 20:33:01 +00:00
eaa536a773
Remove unused variable.
...
llvm-svn: 120836
2010-12-03 19:55:37 +00:00
bc6af0ce91
Reduce t2 ldr/str instructions to the correct t1 versions when there's an
...
immediate offset.
llvm-svn: 120833
2010-12-03 19:47:11 +00:00
d5e6e5459f
fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and Darwin
...
llvm-svn: 120832
2010-12-03 19:40:23 +00:00
f799579ddd
No need to declare EncoderMethod property anymore; just assign to it.
...
llvm-svn: 120831
2010-12-03 19:31:00 +00:00
6423c29e14
Add FIXMEs.
...
llvm-svn: 120824
2010-12-03 18:37:17 +00:00
2a862cd6e1
Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.
...
llvm-svn: 120822
2010-12-03 18:31:03 +00:00
36110d5d1a
Don't overwrite the opcode passed into the T1Special pattern.
...
llvm-svn: 120782
2010-12-03 02:02:58 +00:00
4d8ff86b9e
Add Thumb encoding for some more instructions.
...
llvm-svn: 120780
2010-12-03 01:55:47 +00:00
f0b36a3cfd
The tLDR instruction wasn't encoded properly:
...
<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>
Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.
llvm-svn: 120766
2010-12-03 00:53:22 +00:00
dea4d78fa9
Trailing whitespace.
...
llvm-svn: 120748
2010-12-02 23:05:38 +00:00
cdae9242fa
When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,
...
not thumb2.
llvm-svn: 120711
2010-12-02 16:42:25 +00:00
371e586544
Fix copy/pasto in vmin.f32 encoding.
...
llvm-svn: 120709
2010-12-02 16:30:58 +00:00
ce2bd8d05f
Add support for binary encoding of ARM 'adr' instructions referencing constant
...
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
llvm-svn: 120635
2010-12-02 00:28:45 +00:00
419ea286ee
Fix and re-enable tail call optimization of expanded libcalls.
...
llvm-svn: 120622
2010-12-01 22:59:46 +00:00
fc5c522864
fixing style nit: move class static to global static
...
llvm-svn: 120619
2010-12-01 22:46:50 +00:00
87240d4b9c
Add a post encoder method to the VFP instructions to convert them to the Thumb2
...
encoding if we're in that mode.
llvm-svn: 120608
2010-12-01 21:54:50 +00:00
30eb6c7e71
Use the correct fixup type for ARM VLDR*
...
llvm-svn: 120604
2010-12-01 21:09:40 +00:00
dc35e067c1
Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADR
...
instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
llvm-svn: 120594
2010-12-01 19:47:31 +00:00
943fb60b1f
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
...
llvm-svn: 120589
2010-12-01 19:18:46 +00:00
b5c9cc54d3
kill trailing space
...
llvm-svn: 120586
2010-12-01 19:07:22 +00:00
7f5b475852
10 bits, not 12.
...
llvm-svn: 120584
2010-12-01 18:51:32 +00:00
bfbf357c74
Elaborate on FIXME.
...
llvm-svn: 120552
2010-12-01 04:01:17 +00:00
d0d1329fc8
Move the ARMAsmPrinter class defintiion into a header file.
...
llvm-svn: 120551
2010-12-01 03:45:07 +00:00
901d4d07d8
Remove "comparison of integers of different signs" warning by making the
...
variable unsigned.
llvm-svn: 120541
2010-12-01 02:49:04 +00:00
cbb08ca08c
General cleanups of comments.
...
llvm-svn: 120536
2010-12-01 02:42:55 +00:00
29805961d8
ARM/MC/ELF relocation "hello world" for movw/movt.
...
Lifted adjustFixupValue() from Darwin for sharing w ELF.
Test added
TODO:
refactor ELFObjectWriter::RecordRelocation more.
Possibly share more code with Darwin?
Lots more relocations...
llvm-svn: 120534
2010-12-01 02:40:06 +00:00
9c25894995
Formatting. It's all the rage!
...
llvm-svn: 120533
2010-12-01 02:36:55 +00:00
8ed14ae48a
More refactoring. This time the T1pI pattern.
...
llvm-svn: 120532
2010-12-01 02:28:08 +00:00
119ff7ff04
Refactor load/store handling again. Simplify and make some room for
...
reg+reg handling.
llvm-svn: 120526
2010-12-01 01:40:24 +00:00
d602c2cc19
Initialize an ARMConstantPoolValue field.
...
llvm-svn: 120525
2010-12-01 01:38:58 +00:00
c25545a1a7
s/T1pIEncode/T1pILdStEncode/g
...
s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
7c646b924b
Renaming variables to coincide with documentation. No functionality change.
...
llvm-svn: 120522
2010-12-01 01:32:02 +00:00
490240a5d9
Refactor T1sI and T1sIt encodings into helper classes.
...
llvm-svn: 120518
2010-12-01 01:20:15 +00:00
4915f56669
Refactor the T1sIt encodings into a parent class to get rid of all of the "let"
...
statements.
llvm-svn: 120512
2010-12-01 00:48:44 +00:00
4472801765
Use by-name rather than by-order matching for NEON operands.
...
llvm-svn: 120507
2010-12-01 00:28:25 +00:00
d4b0873c06
Enable sibling call optimization of libcalls which are expanded during
...
legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777
llvm-svn: 120501
2010-11-30 23:55:39 +00:00
05632cb5cc
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
ee48d2daaa
Fix typo.
...
llvm-svn: 120499
2010-11-30 23:51:41 +00:00
38d90de7c3
Trailing whitespace.
...
llvm-svn: 120497
2010-11-30 23:29:24 +00:00
c440e79126
Thanks to JimG for catching this!
...
llvm-svn: 120494
2010-11-30 23:27:18 +00:00
5c51fcda81
Inline classes that were used in only one place.
...
llvm-svn: 120488
2010-11-30 23:16:25 +00:00
a9e3df7aa0
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
8335e8fa63
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
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Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
llvm-svn: 120481
2010-11-30 22:45:47 +00:00
2d3e5c1aec
Fix handling of ARM negative pc-relative fixups for loads and stores.
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llvm-svn: 120480
2010-11-30 22:40:36 +00:00
0dc6246fc0
Provide Thumb2 encodings for a few miscellaneous instructions.
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llvm-svn: 120455
2010-11-30 20:00:01 +00:00
233890547d
Add FIXME
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llvm-svn: 120451
2010-11-30 19:25:56 +00:00
299382e8cb
Add encoding support for Thumb2 PLD and PLI instructions.
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llvm-svn: 120449
2010-11-30 19:19:31 +00:00
78b4efb472
Noticed this on inspection, fix and update some comments.
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llvm-svn: 120447
2010-11-30 19:14:07 +00:00
3b4e2ab5f3
Pseudo-ize ARM MOVPCRX
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llvm-svn: 120442
2010-11-30 18:56:36 +00:00
ebcd9c9258
Provide encodings for a few more load/store variants.
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llvm-svn: 120439
2010-11-30 18:38:28 +00:00
cd5e30f6c6
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
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rdar://8685712
llvm-svn: 120438
2010-11-30 18:30:19 +00:00
811c936ed5
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
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certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
2010-11-30 07:44:32 +00:00
ddce9f3757
Minor cleanups. No functional change.
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llvm-svn: 120372
2010-11-30 00:50:22 +00:00
8294a30d54
s/ARM::BRIND/ARM::BX/g to coincide with r120366.
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llvm-svn: 120371
2010-11-30 00:48:15 +00:00
62718de2b9
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
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able to match this yet.
llvm-svn: 120369
2010-11-30 00:34:08 +00:00
027bd47e3e
Rename BX/BRIND/etc patterns to clarify which is actually the BX instruction
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and which are pseudos.
llvm-svn: 120366
2010-11-30 00:24:05 +00:00
85a8a72d85
Add some encoding for the adr instruction. Labels still need to be finished.
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llvm-svn: 120365
2010-11-30 00:18:30 +00:00
e22c7322b8
Correct Thumb2 encodings for a much wider range of loads and stores.
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llvm-svn: 120364
2010-11-30 00:14:31 +00:00
49408cef39
Make a few more ARM pseudo instructions actually use the PseudoInst base class.
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llvm-svn: 120362
2010-11-30 00:09:06 +00:00
ce3d6ca564
Predicate encoding should be withing {}s. And general cleanup.
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llvm-svn: 120361
2010-11-30 00:08:20 +00:00
795f211418
Predicate encoding should be withing {}s.
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llvm-svn: 120360
2010-11-30 00:05:25 +00:00
318ce7cb3f
Fix the encoding of VLD4-dup alignment.
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The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
llvm-svn: 120358
2010-11-30 00:00:42 +00:00
0b27b68164
Rename VLDnDUP instructions with double-spaced registers
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in an attempt to make things a little more consistent.
llvm-svn: 120357
2010-11-30 00:00:38 +00:00
431ac4ef50
Add support for NEON VLD3-dup instructions.
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The encoding for alignment in VLD4-dup instructions is still a work in progress.
llvm-svn: 120356
2010-11-30 00:00:35 +00:00
9de9a73433
Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions.
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llvm-svn: 120354
2010-11-29 23:51:31 +00:00
0c51bb4b25
Parameterize ARMPseudoInst size property.
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llvm-svn: 120353
2010-11-29 23:48:41 +00:00
cb803b043b
Add a few missing initializers.
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llvm-svn: 120350
2010-11-29 23:41:10 +00:00
32ff5586fc
Nuke trailing whitespace.
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llvm-svn: 120344
2010-11-29 23:18:01 +00:00
9f0356b3cc
Nuke a FIXME. No need to be fancier here, as ARM handles constant pools
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locations and formatting specially. rdar://7353441
llvm-svn: 120343
2010-11-29 23:09:20 +00:00
Jim Grosbach