20480d26e9
Revert r121808 until I can fix the build.
...
llvm-svn: 121815
2010-12-15 00:04:00 +00:00
eda5177ca6
thumb adr fixup needs alignment just like the t2 version.
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llvm-svn: 121812
2010-12-14 23:47:35 +00:00
5ab38b59e6
Comments and cleaning.
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llvm-svn: 121809
2010-12-14 23:42:48 +00:00
00adcd6ed9
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
...
particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0 ]
and not
ldr r2, [r3, r0]
llvm-svn: 121808
2010-12-14 23:40:49 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
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llvm-svn: 121798
2010-12-14 22:28:03 +00:00
6ea3053824
Fix comment.
...
llvm-svn: 121797
2010-12-14 22:26:49 +00:00
ce4f87b3ba
Multiclassify the LDR/STR encoding patterns. The only functionality difference
...
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
d96bd53d04
trailing whitespace
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llvm-svn: 121792
2010-12-14 21:28:29 +00:00
8c1fabe367
Refactor a bit for legibility.
...
llvm-svn: 121790
2010-12-14 21:10:47 +00:00
2fc6561102
trailing whitespace.
...
llvm-svn: 121789
2010-12-14 20:46:39 +00:00
96254146cf
Make sure to propagate the predicate operands for LEApcrel to ADR.
...
llvm-svn: 121788
2010-12-14 20:45:47 +00:00
f636a64bfe
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
...
llvm-svn: 121784
2010-12-14 19:42:53 +00:00
a9b9300bb8
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
...
llvm-svn: 121772
2010-12-14 17:37:16 +00:00
e34793e960
Trailing whitespace
...
llvm-svn: 121769
2010-12-14 16:25:15 +00:00
6dd0c07622
Use the integer scheduling intrinsic for integer loads and stores.
...
llvm-svn: 121765
2010-12-14 12:33:05 +00:00
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
c177813755
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
...
llvm-svn: 121746
2010-12-14 03:22:07 +00:00
6d375e5637
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
...
process cleaner.
llvm-svn: 121735
2010-12-14 00:36:49 +00:00
651eaa02b8
Remove the rest of the *_sfp Neon instruction patterns.
...
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
llvm-svn: 121730
2010-12-13 23:02:37 +00:00
aae0862172
Simplify N2VSPat, removing some unnecessary type arguments.
...
llvm-svn: 121729
2010-12-13 23:02:31 +00:00
9a4d42855d
Revert r121721, which broke buildbots.
...
llvm-svn: 121726
2010-12-13 22:51:08 +00:00
4efa445f3c
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
...
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
llvm-svn: 121721
2010-12-13 22:29:52 +00:00
9c00c014ab
Delete a line that I forgot to revert previously.
...
llvm-svn: 121719
2010-12-13 22:05:55 +00:00
9b3546d877
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
...
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
llvm-svn: 121718
2010-12-13 21:58:05 +00:00
157fec42c9
Use pseudo instructions for 2-register Neon instructions for scalar FP.
...
Partial fix for Radar 8711675.
llvm-svn: 121716
2010-12-13 21:05:52 +00:00
52f522720e
Remove unused instruction class arguments.
...
llvm-svn: 121715
2010-12-13 21:05:44 +00:00
2e51bb4ff0
Generalize BFI isel lowering a bit.
...
llvm-svn: 121714
2010-12-13 20:32:54 +00:00
578074b2f3
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
...
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
llvm-svn: 121710
2010-12-13 19:31:11 +00:00
f588c516b7
Use 32-bit types for 32-bit values.
...
llvm-svn: 121709
2010-12-13 19:25:46 +00:00
3aeb867d74
Trailing whitespace.
...
llvm-svn: 121708
2010-12-13 19:18:13 +00:00
3434575704
(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056
...
llvm-svn: 121606
2010-12-11 04:11:38 +00:00
aecdd871da
Add FIXME
...
llvm-svn: 121598
2010-12-10 23:41:10 +00:00
235c276442
Attempt to get Thumb2 branch fixups working properly.
...
llvm-svn: 121593
2010-12-10 23:02:28 +00:00
7cdd232895
Fix merge error in my last fix to Thumb2 vldr fixups.
...
llvm-svn: 121588
2010-12-10 22:53:48 +00:00
4743d75640
Fixups for Thumb2 vldr's need to have the effective PC aligned as well.
...
llvm-svn: 121587
2010-12-10 22:46:47 +00:00
006ab13b59
The MCFixupKindInfo table needs to be in the order that the enums were
...
declared. Add a note specifying this and spruce up the list a bit.
llvm-svn: 121586
2010-12-10 22:37:19 +00:00
b538a22762
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
...
llvm-svn: 121585
2010-12-10 22:32:08 +00:00
9375d27460
Add float patterns for Neon vld1-lane/dup and vst1-lane operations.
...
llvm-svn: 121583
2010-12-10 22:13:32 +00:00
e1d3322111
Remove unused arguments.
...
llvm-svn: 121582
2010-12-10 22:13:24 +00:00
b0fa127f60
Fix encoding of Thumb1 LDRB and STRB.
...
llvm-svn: 121581
2010-12-10 22:11:13 +00:00
c4a0c29edb
Trailing whitespace.
...
llvm-svn: 121580
2010-12-10 21:57:34 +00:00
68cb7e3552
Fix Thumb2 encodings of STREX and LDREX.
...
llvm-svn: 121579
2010-12-10 21:52:38 +00:00
fc17b5be78
Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999
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llvm-svn: 121525
2010-12-10 21:24:18 +00:00
e69f724935
Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726
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llvm-svn: 121524
2010-12-10 21:05:07 +00:00
e991a6ee5a
More trivial cleanup. No need to define the EncoderMethod property type. Can
...
just assign to it.
llvm-svn: 121523
2010-12-10 20:53:44 +00:00
95bd6b7b62
Tidy up.
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llvm-svn: 121522
2010-12-10 20:51:35 +00:00
c4669edf2c
Trailing whitespace.
...
llvm-svn: 121521
2010-12-10 20:47:29 +00:00
d29b38c893
Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions.
...
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed. Add tests for this, too.
llvm-svn: 121506
2010-12-10 19:37:42 +00:00
bdb7ed16c1
Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR
...
instructions to restore a single register rather than an LDM instruction.
rdar://8754999
llvm-svn: 121498
2010-12-10 18:41:15 +00:00
e119da1146
Thumb unconditional branch binary encoding. rdar://8754994
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llvm-svn: 121496
2010-12-10 18:21:33 +00:00
78485ad65e
Thumb conditional branch binary encodings. rdar://8745367
...
llvm-svn: 121493
2010-12-10 17:13:40 +00:00
c92136ffb6
Fix the leak from r121401 of the Operands erased in the list but not deleted.
...
llvm-svn: 121450
2010-12-10 01:41:56 +00:00
0c4838bab7
Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the
...
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
2010-12-09 21:49:07 +00:00
cb4d8f2e74
Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect,
...
but it gets many more of them correct than it did previously.
llvm-svn: 121414
2010-12-09 21:34:47 +00:00
3ef19d9d48
Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
...
the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.
llvm-svn: 121408
2010-12-09 20:27:52 +00:00
68b27eb9d1
Rename CB/CBZ specific fixup accordingly.
...
llvm-svn: 121404
2010-12-09 19:50:12 +00:00
3164a346e6
Add support for parsing ARM arithmetic instructions that update or don't update
...
the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
llvm-svn: 121401
2010-12-09 19:19:43 +00:00
62b68112da
Rename the encoder method for t_cbtarget to match.
...
llvm-svn: 121399
2010-12-09 19:04:53 +00:00
529c7e8d1f
Thumb needs a few different encoding schemes for branch targets. Rename
...
t_brtarget to be more specific.
llvm-svn: 121398
2010-12-09 19:01:46 +00:00
5fccad84a3
ARM stm/ldm instructions require more than one register in the register list.
...
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460
llvm-svn: 121391
2010-12-09 18:31:13 +00:00
23f8671e05
tidy up.
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llvm-svn: 121371
2010-12-09 16:15:41 +00:00
c0b669f5c0
80 columns.
...
llvm-svn: 121370
2010-12-09 16:14:46 +00:00
817b7cd7b8
Fix encoding of the immediate operands on post-indexed LDR and friends.
...
llvm-svn: 121354
2010-12-09 02:56:12 +00:00
2a2e65c452
Fix up some comments.
...
llvm-svn: 121351
2010-12-09 01:57:45 +00:00
3e6ee1db3e
Fix Thumb2 fixups for ldr.
...
llvm-svn: 121350
2010-12-09 01:51:07 +00:00
6233189713
Add a textual message to the assert.
...
llvm-svn: 121349
2010-12-09 01:23:51 +00:00
ed40288eb4
Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are
...
referencing the stack pointer as they say they are.
llvm-svn: 121347
2010-12-09 01:22:19 +00:00
bd30afe4c2
When using multiple instructions to reference a frame index, make sure to
...
update the opcode when necessary as well as the source register.
llvm-svn: 121346
2010-12-09 01:22:13 +00:00
0b2630c500
The add/sub SP instructions are really pseudos. The assembler should ignore
...
them.
llvm-svn: 121345
2010-12-09 01:21:27 +00:00
eb369f84ec
Remove unused variables
...
llvm-svn: 121343
2010-12-09 01:04:43 +00:00
14e41271b7
Fix typo in Thumb2 branch fixup.
...
llvm-svn: 121342
2010-12-09 01:02:09 +00:00
f75412dec7
Remove extraneous semicolon.
...
llvm-svn: 121338
2010-12-09 00:51:54 +00:00
c4d333f02a
Attempt to make the bit-twiddling readable resulted in the binary value being
...
overwritten.
llvm-svn: 121337
2010-12-09 00:44:33 +00:00
3392bfc8f3
The BLX instruction is encoded differently than the BL, because why not? In
...
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
2010-12-09 00:39:08 +00:00
302d5fd0d8
Fix Thumb2 BCC encoding and fixups.
...
llvm-svn: 121329
2010-12-09 00:27:41 +00:00
e296ee830a
Style nit and whitespace cleanup
...
llvm-svn: 121317
2010-12-08 23:35:25 +00:00
9672c9a793
Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME
...
for more thorough cleanup.
llvm-svn: 121315
2010-12-08 23:30:19 +00:00
a5c666654e
Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends.
...
llvm-svn: 121314
2010-12-08 23:24:29 +00:00
ba8b6d9a1c
Removed dead comment.
...
llvm-svn: 121313
2010-12-08 23:19:44 +00:00
c79c5f6e8c
ARM/MC/ELF TPsoft is now a proper pseudo inst.
...
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
llvm-svn: 121312
2010-12-08 23:14:44 +00:00
e829c674bb
T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead.
...
llvm-svn: 121311
2010-12-08 23:13:01 +00:00
fd0e4c0fe9
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434
...
llvm-svn: 121310
2010-12-08 23:12:09 +00:00
51937f9963
Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434
...
llvm-svn: 121309
2010-12-08 23:04:16 +00:00
a7d6aa902a
Support the "target" encodings for the CB[N]Z instructions.
...
llvm-svn: 121308
2010-12-08 23:01:43 +00:00
7f3e9150d0
Fix an obvious cut-n-paste error.
...
llvm-svn: 121307
2010-12-08 23:01:18 +00:00
663e4ce357
Add operand encoding for Thumb2 addw SP + imm. rdar://8745434
...
llvm-svn: 121305
2010-12-08 22:50:19 +00:00
47e3cc54f8
Parameterize opcode encoding bits for Thumb2 extended precision integer
...
multiply instructions.
llvm-svn: 121301
2010-12-08 22:38:41 +00:00
c3b0b10708
Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555
...
llvm-svn: 121297
2010-12-08 22:29:28 +00:00
572e56dfb2
Simplify T2 operand assignment notation a bit. No need to specify a bit range
...
for the source field when it's the whole thing that's being referenced.
llvm-svn: 121291
2010-12-08 22:10:43 +00:00
3c68561453
Tweak ARM fixup value adjustments for Thumb to better handle the half-word
...
ordering of thumb mode.
llvm-svn: 121280
2010-12-08 20:32:07 +00:00
00067fb147
Generalize PostRAHazardRecognizer so it can be used in any pass for
...
both forward and backward scheduling. Rename it to
ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer
division from the scoreboard's critical path.
llvm-svn: 121274
2010-12-08 20:04:29 +00:00
dae32fd206
Improve comment.
...
llvm-svn: 121272
2010-12-08 19:31:11 +00:00
d18f98b969
Add initializer.
...
llvm-svn: 121262
2010-12-08 15:36:45 +00:00
9d54ae6332
Add comments.
...
llvm-svn: 121238
2010-12-08 06:29:02 +00:00
8a6449c46e
Add support for loading from a constant pool.
...
llvm-svn: 121226
2010-12-08 01:57:09 +00:00
87055ed6f4
Let target asm backends see assembler flags as they go by. Use that to handle
...
thumb vs. arm mode differences in WriteNopData().
llvm-svn: 121219
2010-12-08 01:16:55 +00:00
72ce453c73
Simplify the byte reordering logic slightly.
...
llvm-svn: 121216
2010-12-08 00:21:33 +00:00
0f7142d808
VLDR fixups need special handling under Thumb. While the encoding is the same,
...
the order of the bytes in the data stream is flipped around.
llvm-svn: 121215
2010-12-08 00:18:36 +00:00
56de7c2773
Fix a warning about a variable which is only used in an assertion.
...
llvm-svn: 121206
2010-12-07 23:26:21 +00:00
f09c44c7ab
Cleanup in the Darwin end. No functionality change.
...
llvm-svn: 121198
2010-12-07 23:11:00 +00:00
Bill Wendling