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4088 Commits

Author SHA1 Message Date
Andrew Trick c416ba612b whitespace 
llvm-svn: 122539
 2010-12-24 04:28:06 +00:00
Jim Grosbach ffaea0f017 Use a StringSwitch<> instead of a manually constructed string matcher. 
llvm-svn: 122530
 2010-12-24 00:03:39 +00:00
Jim Grosbach 545858d209 Remove dead patterns. 
llvm-svn: 122524
 2010-12-23 23:20:13 +00:00
Jim Grosbach bcfa4a945a Recognize a few more documented register name aliases for ARM in the asm lexer. 
llvm-svn: 122523
 2010-12-23 23:19:54 +00:00
Bob Wilson 36be00ceb3 Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions. 
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.

llvm-svn: 122521
 2010-12-23 22:45:49 +00:00
Chris Lattner 2a0a3b43d7 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Jim Grosbach 8c48503baa Trailing whitespace. 
llvm-svn: 122456
 2010-12-22 23:26:02 +00:00
Bob Wilson 1a20c2aedd Add ARM-specific DAG combining to cast i64 vector element load/stores to f64. 
Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register.  Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up.  Radar 8755338.

llvm-svn: 122319
 2010-12-21 06:43:19 +00:00
Eric Christopher c874f6c9ff Arm and thumb call instructions are also in different orders. 
Fixes rdar://8782223

llvm-svn: 122313
 2010-12-21 03:50:43 +00:00
Chris Lattner 3e5fbd74ed rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for 
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
 2010-12-21 02:38:05 +00:00
Eric Christopher 6df5ff8ce6 If we're not using reg+reg offset we're using reg+imm, set the opcode 
to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.

Fixes part of rdar://8782207

llvm-svn: 122307
 2010-12-21 02:12:07 +00:00
Bill Wendling cdcc4fc048 Fix a copy-pasto. When the tBR_JTr instruction was converted to using the 
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>

llvm-svn: 122303
 2010-12-21 01:57:15 +00:00
Bill Wendling 18581a4ac0 Comment cleanups. 
llvm-svn: 122302
 2010-12-21 01:54:40 +00:00
Rafael Espindola 8396dd0893 Remove the MCObjectFormat class. 
llvm-svn: 122147
 2010-12-18 05:37:28 +00:00
Rafael Espindola fdaae0d16f Move some data to the TargetWriter. 
llvm-svn: 122134
 2010-12-18 03:27:34 +00:00
Bill Wendling 429bb1e2cc r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to 
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.

There is a test case, but unfortunately it's sensitive to random code changes.

<rdar://problem/8782223>

llvm-svn: 122131
 2010-12-18 02:13:59 +00:00
Bill Wendling a4dda53686 RemoveUnusedCPEntries can change things. Track it. 
llvm-svn: 122129
 2010-12-18 01:53:06 +00:00
Bob Wilson eda2a9ec89 Rearrange some Neon multiclasses. No functional changes. 
llvm-svn: 122119
 2010-12-18 00:42:58 +00:00
Bob Wilson 00871c71e9 Fix result type of Neon floating-point comparisons against zero. 
The result vector elements are always integers.  Radar 8782191.

llvm-svn: 122112
 2010-12-18 00:04:33 +00:00
Bob Wilson f268d0303b Add some missing entries in ARMTargetLowering::getTargetNodeName. 
llvm-svn: 122111
 2010-12-18 00:04:26 +00:00
Bill Wendling 3fff1fd49b During local stack slot allocation, the materializeFrameBaseRegister function 
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>

llvm-svn: 122104
 2010-12-17 23:09:14 +00:00
Bob Wilson a7dabbd2cf Avoid report_fatal_error in ARM's PrintAsmOperand method. 
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

llvm-svn: 122100
 2010-12-17 23:06:42 +00:00
Jim Grosbach 97f1de7347 If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with 
a partial value. rdar://8782954

llvm-svn: 122078
 2010-12-17 19:03:02 +00:00
Jim Grosbach 06ab8b648c Add bits 31-28 to the Thumb2 encoding of TBB/TBH. 
llvm-svn: 122076
 2010-12-17 18:42:56 +00:00
Jim Grosbach 4416dfa8fb Handle 2 and 4 byte data blob fixup values for ARM. 
llvm-svn: 122075
 2010-12-17 18:39:10 +00:00
Rafael Espindola 6b5e56c2b1 Stub out explicit MCELFObjectTargetWriter interface. 
llvm-svn: 122067
 2010-12-17 17:45:22 +00:00
Rafael Espindola f0e24d426a Move createELFObjectWriter to its own header. 
llvm-svn: 122064
 2010-12-17 16:59:53 +00:00
Daniel Dunbar e054a782fc MC/ARM: Use aggressive symbol folding (important for jump tables, for example). 
llvm-svn: 122044
 2010-12-17 06:00:24 +00:00
Daniel Dunbar d2867f13a0 MC/Target: Remove HasScatteredSymbols target hook variable, which has been 
superceded and was effectively dead.

llvm-svn: 122024
 2010-12-17 02:06:08 +00:00
Bob Wilson 261aad8e16 Use PairDRegs to implement ConcatVectors. No functionality change. 
llvm-svn: 122017
 2010-12-17 01:21:08 +00:00
Jim Grosbach b5743b9d76 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974 
llvm-svn: 121990
 2010-12-16 19:11:16 +00:00
Daniel Dunbar 03fcccbb47 MC/Mach-O: Lift some MachObjectWriter arguments into the target specific 
interface.

llvm-svn: 121981
 2010-12-16 17:21:02 +00:00
Daniel Dunbar 8888a9604d MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface. 
llvm-svn: 121973
 2010-12-16 16:09:19 +00:00
Daniel Dunbar 73b8713d7c MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h. 
llvm-svn: 121971
 2010-12-16 16:08:33 +00:00
Daniel Dunbar 0c9d9fdd81 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of 
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953
 2010-12-16 03:20:06 +00:00
Matt Beaumont-Gay e9afc740a8 Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang 
(see PR4579).

llvm-svn: 121939
 2010-12-16 01:34:26 +00:00
Bill Wendling 9613a09e5c Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for 
it. I.e., it was always an immediate value.

llvm-svn: 121932
 2010-12-16 00:50:33 +00:00
Bill Wendling 637813a258 Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi 
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.

llvm-svn: 121931
 2010-12-16 00:49:54 +00:00
Bill Wendling f5b17c32d2 Add encodings for Thumb1 Spill and Restore pseudos. 
llvm-svn: 121929
 2010-12-16 00:38:41 +00:00
Jim Grosbach bfef309d11 Thumb1 had two patterns for the same load-from-constant-pool instruction. 
Canonicalize on tLDRpci and remove tLDRcp.

llvm-svn: 121920
 2010-12-15 23:52:36 +00:00
Eric Christopher 347f4c32e8 Don't handle -arm-long-calls in fast isel for now. 
llvm-svn: 121919
 2010-12-15 23:47:29 +00:00
Bill Wendling 7d3bde98f1 If we're changing the frame register to a physical register other than SP, we 
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.

llvm-svn: 121915
 2010-12-15 23:32:27 +00:00
Bill Wendling 6217ecd634 Whitespace cleanups. 
llvm-svn: 121914
 2010-12-15 23:31:24 +00:00
Bob Wilson fa27a8621c Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
 2010-12-15 22:14:12 +00:00
Jim Grosbach 23477c2ee5 Tweak a few pseudo-inst pattern base classes. 
llvm-svn: 121878
 2010-12-15 19:03:16 +00:00
Jim Grosbach d42257ceef The new t2LEApcrel* pseudo instructions need the size specified. 
rdar://8768390

llvm-svn: 121876
 2010-12-15 18:48:45 +00:00
Owen Anderson 622ad5170b Implement cleanups suggested by Daniel. 
llvm-svn: 121875
 2010-12-15 18:48:27 +00:00
Bill Wendling 03e7576dee Add fixups for Thumb LDR/STR instructions. 
llvm-svn: 121858
 2010-12-15 08:51:02 +00:00
Bill Wendling 832a5daab5 Reapply r121808 now that the missing patterns have been supplied. 
llvm-svn: 121820
 2010-12-15 01:03:19 +00:00
Bill Wendling 1171e9e81d Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.

llvm-svn: 121819
 2010-12-15 00:58:57 +00:00