326a03732e
Some Mips minor fixes
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Added support for mips little endian arch => mipsel
llvm-svn: 51923
2008-06-04 01:45:25 +00:00
ed6e34fe41
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
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llvm-svn: 48995
2008-03-31 20:40:39 +00:00
0f760dfe09
Fix "Control reaches the end of non-void function" warnings,
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patch by David Chisnall.
llvm-svn: 48963
2008-03-30 18:22:13 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
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llvm-svn: 46930
2008-02-10 18:45:23 +00:00
1dea406e73
Trivial patch to fix two warnings, please pull into llvm 2.2
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llvm-svn: 46243
2008-01-22 04:47:47 +00:00
2a3be7bb6c
Move even more functionality from MRegisterInfo into TargetInstrInfo.
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Some day I'll get it all moved over...
llvm-svn: 45672
2008-01-07 01:35:02 +00:00
eee14601b1
Move some more instruction creation methods from RegisterInfo into InstrInfo.
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llvm-svn: 45484
2008-01-01 21:11:32 +00:00
7a73ae9a86
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
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Machine-level API cleanup instigated by Chris.
llvm-svn: 45470
2007-12-31 06:32:00 +00:00
a5bb370aa4
Add new shorter predicates for testing machine operands for various types:
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e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.
Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.
llvm-svn: 45464
2007-12-30 23:10:15 +00:00
5c4637816e
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
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llvm-svn: 45453
2007-12-30 20:49:49 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
bb26301864
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
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the stored register is killed.
llvm-svn: 44600
2007-12-05 03:14:33 +00:00
f45a1d623c
Remove redundant foldMemoryOperand variants and other code clean up.
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llvm-svn: 44517
2007-12-02 08:30:39 +00:00
69fda0a716
Allow some reloads to be folded in multi-use cases. Specifically testl r, r -> cmpl [mem], 0.
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llvm-svn: 44479
2007-12-01 02:07:52 +00:00
7a7085f6d3
Add parameter to getDwarfRegNum to permit targets
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to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.
llvm-svn: 44056
2007-11-13 19:13:01 +00:00
4edfea438a
Use TableGen to emit information for dwarf register numbers.
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This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
llvm-svn: 43997
2007-11-11 19:50:10 +00:00
3e0d030dad
Added support for PIC code with "explicit relocations" *only*.
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Removed all macro code for PIC (goodbye "la").
Support tested with shootout bench.
llvm-svn: 43697
2007-11-05 03:02:32 +00:00
463e2ab0ac
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
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- Fix some copy+paste bugs.
llvm-svn: 43153
2007-10-18 22:40:57 +00:00
aa9a225699
Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister public interface.
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llvm-svn: 43150
2007-10-18 21:29:24 +00:00
66d9572ced
Position Independent Code (PIC) support [3]
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llvm-svn: 42780
2007-10-09 03:15:11 +00:00
f4cf5dcdd2
- Added a few target hooks to generate load / store instructions from / to any
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address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
llvm-svn: 42621
2007-10-05 01:32:41 +00:00
c1e4e3743b
Allow copyRegToReg to emit cross register classes copies.
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Tested with "make check"!
llvm-svn: 42346
2007-09-26 06:25:56 +00:00
43318839c9
Added method to get Mips register numbers
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Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack.
Stack offset calculation bug fixed!
llvm-svn: 41529
2007-08-28 05:13:42 +00:00
eabe61b080
Fixed stack frame addressing bug
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llvm-svn: 41160
2007-08-18 02:19:09 +00:00
94b5a80b93
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
6c8c748e4d
Added support for framepointer
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Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!
llvm-svn: 39763
2007-07-11 23:21:31 +00:00
35e43c49b0
Initial Mips support, here we go! =)
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- Modifications from the last patch included
(issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.
llvm-svn: 37461
2007-06-06 07:42:06 +00:00
Bruno Cardoso Lopes