97f8adffff
Correct the implicit-defs information for indirect and direct calls.
...
You can't have implicit defs that overlap explicit defs, or implicit
defs that alias one another.
llvm-svn: 17894
2004-11-16 07:32:09 +00:00
f242979cd0
Simplify namespaces
...
llvm-svn: 17870
2004-11-16 04:47:33 +00:00
6b7652fae5
Remove a dead function, which died when we got GAS emission working (phwew,
...
hold your nose!)
llvm-svn: 17869
2004-11-16 04:34:29 +00:00
c927072b50
Implement a simple FIXME: if we are emitting a basic block address that has
...
already been emitted, we don't have to remember it and deal with it later,
just emit it directly.
llvm-svn: 17868
2004-11-16 04:30:51 +00:00
2e182fc39b
* Merge some win32 ifdefs together
...
* Get rid of "emitMaybePCRelativeValue", either we want to emit a PC relative
value or not: drop the maybe BS. As it turns out, the only places where
the bool was a variable coming in, the bool was a dynamic constant.
llvm-svn: 17867
2004-11-16 04:21:18 +00:00
9cc2dac7c1
Add debug-only=jit printout, so we see when lazily resolved symbols are
...
set up.
llvm-svn: 17862
2004-11-15 23:16:55 +00:00
34b754d99b
Simplify and rearrange long shift code
...
llvm-svn: 17861
2004-11-15 23:16:34 +00:00
a8c99d4daf
Add BCTR and LWZU instruction opcodes
...
llvm-svn: 17851
2004-11-15 21:20:09 +00:00
55157f0865
Update list of failing Benchmarks.
...
llvm-svn: 17823
2004-11-15 05:57:26 +00:00
9dcb2fe161
Expand Defs to encompass all the possibly-call-clobbered regs.
...
llvm-svn: 17822
2004-11-15 05:56:53 +00:00
7f245d47c5
GhostLinkage should not reach asm printing stage
...
llvm-svn: 17750
2004-11-14 21:03:49 +00:00
e225fa12ab
Handle GhostLinkage (should not ever reach the assembly printing stage!)
...
llvm-svn: 17749
2004-11-14 21:03:30 +00:00
8b8ba9fcf7
Fix build on Linux/PowerPC64 using SuSE GCC (#undef PPC)
...
llvm-svn: 17744
2004-11-14 20:34:01 +00:00
e13c960415
Fix problem with insertion point for ADJCALLSTACKDOWN.
...
llvm-svn: 17733
2004-11-14 06:32:08 +00:00
a281ebc490
Update lists of failing unit tests.
...
Exclude bigfib, so that we effectively exclude all C++ benchmarks.
Update to-do list: mention va_start.
llvm-svn: 17732
2004-11-14 06:32:07 +00:00
347a000be6
Fix NotTest - round up extraStack to the nearest doubleword, if it is
...
not zero.
llvm-svn: 17728
2004-11-14 05:19:00 +00:00
e90176e171
Update failing Benchmarks; point out that I'm skipping Shootout-C++.
...
llvm-svn: 17725
2004-11-14 04:43:12 +00:00
18b6015b11
Update expected UnitTests failures.
...
llvm-svn: 17723
2004-11-14 03:22:08 +00:00
e6b47514a3
Rewrite outgoing arg handling to handle more weird corner cases.
...
llvm-svn: 17722
2004-11-14 03:22:07 +00:00
07097e12d5
Support UndefValue emission.
...
llvm-svn: 17721
2004-11-14 03:22:05 +00:00
56c4c99cca
Don't print unneeded labels
...
llvm-svn: 17714
2004-11-13 23:27:11 +00:00
073f6ca344
Hack around stupidity in GCC, fixing Burg with the CBE and
...
CBackend/2004-11-13-FunctionPointerCast.llx
llvm-svn: 17710
2004-11-13 22:21:56 +00:00
049d33a717
shld is a very high latency operation. Instead of emitting it for shifts of
...
two or three, open code the equivalent operation which is faster on athlon
and P4 (by a substantial margin).
For example, instead of compiling this:
long long X2(long long Y) { return Y << 2; }
to:
X3_2:
movl 4(%esp), %eax
movl 8(%esp), %edx
shldl $2, %eax, %edx
shll $2, %eax
ret
Compile it to:
X2:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
shrl $30, %edx
leal (%edx,%ecx,4), %edx
shll $2, %eax
ret
Likewise, for << 3, compile to:
X3:
movl 4(%esp), %eax
movl 8(%esp), %ecx
movl %eax, %edx
shrl $29, %edx
leal (%edx,%ecx,8), %edx
shll $3, %eax
ret
This matches icc, except that icc open codes the shifts as adds on the P4.
llvm-svn: 17707
2004-11-13 20:48:57 +00:00
ef6bd92a8c
Add missing check
...
llvm-svn: 17706
2004-11-13 20:04:38 +00:00
8d521bb16e
Compile:
...
long long X3_2(long long Y) { return Y+Y; }
int X(int Y) { return Y+Y; }
into:
X3_2:
movl 4(%esp), %eax
movl 8(%esp), %edx
addl %eax, %eax
adcl %edx, %edx
ret
X:
movl 4(%esp), %eax
addl %eax, %eax
ret
instead of:
X3_2:
movl 4(%esp), %eax
movl 8(%esp), %edx
shldl $1, %eax, %edx
shll $1, %eax
ret
X:
movl 4(%esp), %eax
shll $1, %eax
ret
llvm-svn: 17705
2004-11-13 20:03:48 +00:00
04570265a5
Correct the name of stosd for the AT&T syntax:
...
It's stosl (l for long == 32 bit).
llvm-svn: 17658
2004-11-10 04:48:15 +00:00
1164955bf1
Allow hbd to be bugpointable on darwin by fixing common and linkonce codegen
...
llvm-svn: 17637
2004-11-09 04:01:18 +00:00
0822032c95
Put int the getReg cast optimization from x86 so that we generate fewer
...
move instructions for the register allocator to coalesce.
llvm-svn: 17608
2004-11-08 02:25:40 +00:00
f5f0b6b6b0
Disable bogus cast elimination when the cast is used by a setcc instruction.
...
llvm-svn: 17583
2004-11-07 20:23:42 +00:00
b3ba9319f1
Decompose* is V9 specific, make it internal
...
llvm-svn: 17547
2004-11-07 00:43:24 +00:00
3dadadc837
Move this file from lib/Transforms/Scalar
...
llvm-svn: 17544
2004-11-07 00:39:09 +00:00
ab79288e37
Fix compilation problem; make the cast and the LHS be the same type.
...
llvm-svn: 17488
2004-11-05 16:17:06 +00:00
429aaa5855
Quiet VC++ warnings
...
llvm-svn: 17484
2004-11-05 04:50:59 +00:00
bff3d4abf0
Thanks to sabre for pointing out that we were incorrectly codegen'ing
...
int test(int x) { return 32768 - x; }
Fixed by teaching the function that checks a constant's validity to be used
as an immediate argument about subtract-from instructions.
llvm-svn: 17476
2004-11-04 19:43:18 +00:00
0da246f535
Handle "call" operands of type long/ulong passed in registers.
...
llvm-svn: 17464
2004-11-04 00:27:04 +00:00
cff3b41e95
Fix this function to not say that longs have 8-byte alignment on X86/PPC.
...
This method is really a gross hack, but at least we can make it work on
the targets we support right now.
This bug fix stops a crash in a testcase reduced from 176.gcc
llvm-svn: 17443
2004-11-02 22:18:18 +00:00
444be61ea6
Added gross hacks such as creating my own def-use map, and picking on Instruction that I can add all my TmpInstructions to its MCFI.
...
llvm-svn: 17441
2004-11-02 21:04:56 +00:00
99d7bb3378
Fix a warning
...
llvm-svn: 17431
2004-11-02 15:27:57 +00:00
720eb217a7
Add placeholder variable to make Win32 work, applied for Morten Ofstad
...
llvm-svn: 17406
2004-11-01 20:10:20 +00:00
f88808ae43
Internalize variable names to prevent recursive assignment. Cleanup docs.
...
llvm-svn: 17359
2004-10-30 09:19:36 +00:00
ddebd1eeaa
Fixed bug with infinite epilogues.
...
Fixed issue with generating the partial order. It now adds the nodes not in recurrences in sets for each connected component.
llvm-svn: 17351
2004-10-30 00:39:07 +00:00
b87e08e0ef
Change name of target lib to conform to new naming scheme.
...
llvm-svn: 17347
2004-10-29 21:57:16 +00:00
6254a798ca
Remove dependency on MRegisterInfo::getRegClass
...
llvm-svn: 17346
2004-10-29 21:42:27 +00:00
57cbe39d1e
Change Library Names Not To Conflict With Others When Installed
...
llvm-svn: 17286
2004-10-27 23:18:45 +00:00
a2b117c68a
Move destructor out of line to avoid vtable emission in every file that includes the header. Thanks to sabre.
...
llvm-svn: 17278
2004-10-27 06:00:53 +00:00
c193790dbb
Fix the build by eliminating some more dead code. That'll learn me not to listen to Reid
...
llvm-svn: 17275
2004-10-27 05:44:23 +00:00
7fed324ffc
Remove include of MRegisterInfo.h, since it is already included by
...
SkeletonGenRegisterInfo.h.inc
llvm-svn: 17245
2004-10-26 06:04:23 +00:00
dd8f1d8b77
Remove file that is no longer used, and move include of MRegisterInfo.h
...
from PowerPCFrameInfo.h to PowerPCAsmPrinter.cpp where it is actually
needed.
llvm-svn: 17244
2004-10-26 06:02:38 +00:00
47b9d33f5b
Eliminate usage of MRegisterInfo::getRegClass(physreg)
...
llvm-svn: 17240
2004-10-26 05:40:45 +00:00
4c6e1d694c
Update to-do list
...
llvm-svn: 17235
2004-10-26 04:10:53 +00:00
26feb4f6d8
Fix treecc. Also fix a latent bug in emitBinaryConstOperation that would
...
allow and const, 0 to be incorrectly codegen'd into a rlwinm instruction.
llvm-svn: 17234
2004-10-26 03:48:25 +00:00
ff43ef3cc5
Disable the JIT until it can sorta kinda work.
...
llvm-svn: 17230
2004-10-25 20:53:41 +00:00
21c6c41dcc
Remove dead assert
...
llvm-svn: 17221
2004-10-25 19:04:01 +00:00
7eeed938bf
Removed dead method, printPHICopiesForSuccessors().
...
llvm-svn: 17216
2004-10-25 18:41:50 +00:00
a564e9e0ba
Modified switch generation so that only the phi values associated with the
...
destination basic block are copied.
llvm-svn: 17212
2004-10-25 18:30:09 +00:00
74b7c1f3e0
Implement more complete and correct codegen for bitfield inserts, as tested
...
by the recently committed rlwimi.ll test file. Also commit initial code
for bitfield extract, although it is turned off until fully debugged.
llvm-svn: 17207
2004-10-24 10:33:30 +00:00
9ce0da9e90
* Correctly handle the MovePCtoLR pseudo-instr with a bl to next instr
...
* Stop the confusion of using rv and Addr for global addresses: just use rv
llvm-svn: 17195
2004-10-23 23:47:34 +00:00
f1f6270708
Add BA, BL, and BLA opcodes
...
llvm-svn: 17193
2004-10-23 20:29:24 +00:00
421c3c1ec4
* Do not emit IMPLICIT_DEF pseudo-instructions
...
* Convert register numbers from their opcode value to the real value, e.g.
PPC::R1 => 1 and PPC::F1 => 1
* Add correct handling of loading of global values which are PC-relative --
implement ha16() and lo16()
llvm-svn: 17190
2004-10-23 18:28:01 +00:00
15b0fb5678
DForm_1, particularly used by store instructions, needs the immediate operand to
...
be listed second as that is how the instructions are usually created (and is the
correct asm syntax) so that it's assembled correctly from its constituents
llvm-svn: 17183
2004-10-23 06:08:38 +00:00
e882d30aa1
Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
...
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.
llvm-svn: 17182
2004-10-23 06:05:49 +00:00
55a3ccd035
The value of the XO field for MFLR and MFCTR is 339, not 399
...
llvm-svn: 17181
2004-10-23 05:38:55 +00:00
101d5d62d5
Remove extraneous blank line
...
llvm-svn: 17180
2004-10-23 04:59:22 +00:00
cea2e46821
Align function arguments in function headers
...
llvm-svn: 17178
2004-10-23 04:58:32 +00:00
6cadac8f43
Kill casts from integer types to unsigned byte, when the cast was only used
...
as the shift amount operand to a shift instruction. This was causing us to
emit unnecessary clear operations for code such as:
int foo(int x) { return 1 << x; }
llvm-svn: 17175
2004-10-23 00:50:23 +00:00
4755617619
Clean up the output from this makefile so its not verbose.
...
llvm-svn: 17173
2004-10-22 23:24:39 +00:00
e60a3fb063
Adjust rules for building .inc files due to Reid's changes of Makefile.rules
...
llvm-svn: 17169
2004-10-22 22:16:24 +00:00
30d8baea8d
Adjust to changes in Makefile.rules
...
llvm-svn: 17167
2004-10-22 21:02:08 +00:00
c1c320c335
We won't use automake
...
llvm-svn: 17155
2004-10-22 03:35:04 +00:00
a6ecf271db
Remove debug code emitter from the JIT
...
llvm-svn: 17151
2004-10-21 03:07:38 +00:00
757cc0e84c
Make this compile.
...
llvm-svn: 17150
2004-10-21 02:44:16 +00:00
2beb63a65a
* Added basic support for JITing functions, basic blocks, instruction encoding,
...
including registers, constants, and partial support for global addresses
* The JIT is disabled by default to allow building llvm-gcc, which wants to test
running programs during configure
llvm-svn: 17149
2004-10-21 01:42:02 +00:00
86b5f8075c
Don't clear or sign extend bool->int. This fires a few dozen times on the test suite
...
llvm-svn: 17147
2004-10-20 21:55:41 +00:00
85b380582e
Small performance improvement in generated C code:
...
Instead of unconditionally copying all phi node values into temporaries for
all successor blocks, generate code that will determine what successor
block will be called and then copy only those phi node values needed by
the successor block.
This seems to cut down namd execution time from being 8% higher than GCC to
4% higher than GCC.
llvm-svn: 17144
2004-10-20 14:38:39 +00:00
e2ada0413e
* Add baseline structural JIT code, but disable the JIT to allow llvm-gcc builds
...
- Support added for functions, basic blocks, constant pool, constants,
registers, and some basic support for globals, all untested
* Turn assert()s into abort()s so that unimplemented functions fail in release
llvm-svn: 17143
2004-10-19 19:49:42 +00:00
f3499acc16
Simplify mapping info generation. In particular, the LLVM-to-MachineInstr map
...
is no longer emitted, and we do not reference any MachineCodeForInstruction
information.
llvm-svn: 17138
2004-10-19 05:15:21 +00:00
6a11a75f31
Initial automake generated Makefile template
...
llvm-svn: 17136
2004-10-18 23:55:41 +00:00
fbc070bfdc
Improve compatibility with VC++, patch contributed by Morten Ofstad!
...
llvm-svn: 17126
2004-10-18 15:54:17 +00:00
53058663aa
Print a semicolon for the unreacahble instruction. This fixes problems
...
where C requires semicolons in some cases to indicate null statements.
llvm-svn: 17107
2004-10-17 23:49:11 +00:00
844186b8b4
Generate correct stubs for weak-linked symbols
...
llvm-svn: 17101
2004-10-17 23:01:34 +00:00
621c413a1b
The first hunk corrects a bug when printing undef null values. We would print
...
0->field, which is illegal. Now we print ((foo*)0)->field.
The second hunk is an optimization to not print undefined phi values.
llvm-svn: 17094
2004-10-17 17:48:59 +00:00
068555314b
Don't print stuff out from the code generator. This broke the JIT horribly
...
last night. :) bork!
llvm-svn: 17093
2004-10-17 17:40:50 +00:00
f476d84b69
Make the library name SparcV9 specific
...
llvm-svn: 17089
2004-10-17 15:01:12 +00:00
b7c9d5444b
Consolidate the definitions
...
llvm-svn: 17088
2004-10-17 15:00:26 +00:00
de028a4a69
PPC32GenCodeEmitter instead of PowerPCGenCodeEmitter
...
llvm-svn: 17087
2004-10-17 14:59:38 +00:00
839abf57a6
Rewrite support for cast uint -> FP. In particular, we used to compile this:
...
double %test(uint %X) {
%tmp.1 = cast uint %X to double ; <double> [#uses=1]
ret double %tmp.1
}
into:
test:
sub %ESP, 8
mov %EAX, DWORD PTR [%ESP + 12]
mov %ECX, 0
mov DWORD PTR [%ESP], %EAX
mov DWORD PTR [%ESP + 4], %ECX
fild QWORD PTR [%ESP]
add %ESP, 8
ret
... which basically zero extends to 8 bytes, then does an fild for an
8-byte signed int.
Now we generate this:
test:
sub %ESP, 4
mov %EAX, DWORD PTR [%ESP + 8]
mov DWORD PTR [%ESP], %EAX
fild DWORD PTR [%ESP]
shr %EAX, 31
fadd DWORD PTR [.CPItest_0 + 4*%EAX]
add %ESP, 4
ret
.section .rodata
.align 4
.CPItest_0:
.quad 5728578726015270912
This does a 32-bit signed integer load, then adds in an offset if the sign
bit of the integer was set.
It turns out that this is substantially faster than the preceeding sequence.
Consider this testcase:
unsigned a[2]={1,2};
volatile double G;
void main() {
int i;
for (i=0; i<100000000; ++i )
G += a[i&1];
}
On zion (a P4 Xeon, 3Ghz), this patch speeds up the testcase from 2.140s
to 0.94s.
On apoc, an athlon MP 2100+, this patch speeds up the testcase from 1.72s
to 1.34s.
Note that the program takes 2.5s/1.97s on zion/apoc with GCC 3.3 -O3
-fomit-frame-pointer.
llvm-svn: 17083
2004-10-17 08:01:28 +00:00
112fd88a05
Unify handling of constant pool indexes with the other code paths, allowing
...
us to use index registers for CPI's
llvm-svn: 17082
2004-10-17 07:49:45 +00:00
af19d396ac
Give the asmprinter the ability to print memrefs with a constant pool index,
...
index reg and scale
llvm-svn: 17081
2004-10-17 07:16:32 +00:00
653d8663fe
fold:
...
%X = and Y, constantint
%Z = setcc %X, 0
instead of emitting:
and %EAX, 3
test %EAX, %EAX
je .LBBfoo2_2 # UnifiedReturnBlock
We now emit:
test %EAX, 3
je .LBBfoo2_2 # UnifiedReturnBlock
This triggers 581 times on 176.gcc for example.
llvm-svn: 17080
2004-10-17 06:10:40 +00:00
e234a21488
All of these labels are off by one now that the unreachable instruction exists
...
llvm-svn: 17079
2004-10-17 05:37:47 +00:00
2c873ca365
Implement bitfield insert by recognizing the following pattern:
...
1. optional shift left
2. and x, immX
3. and y, immY
4. or z, x, y
==> rlwimi z, x, y, shift, mask begin, mask end
where immX == ~immY and immX is a run of set bits. This transformation
fires 32 times on voronoi, once on espresso, and probably several
dozen times on external benchmarks such as gcc.
To put this in terms of actual code generated for
struct B { unsigned a : 3; unsigned b : 2; };
void storeA (struct B *b, int v) { b->a = v;}
void storeB (struct B *b, int v) { b->b = v;}
Old:
_storeA:
rlwinm r2, r4, 0, 29, 31
lwz r4, 0(r3)
rlwinm r4, r4, 0, 0, 28
or r2, r4, r2
stw r2, 0(r3)
blr
_storeB:
rlwinm r2, r4, 3, 0, 28
rlwinm r2, r2, 0, 27, 28
lwz r4, 0(r3)
rlwinm r4, r4, 0, 29, 26
or r2, r2, r4
stw r2, 0(r3)
blr
New:
_storeA:
lwz r2, 0(r3)
rlwimi r2, r4, 0, 29, 31
stw r2, 0(r3)
blr
_storeB:
lwz r2, 0(r3)
rlwimi r2, r4, 3, 27, 28
stw r2, 0(r3)
blr
llvm-svn: 17078
2004-10-17 05:19:20 +00:00
f6666db032
I forgot that sparc no longer uses the shared asmwriter. Give it support
...
for undef.
llvm-svn: 17075
2004-10-17 02:44:45 +00:00
37b138a00b
Add support for unreachable and undef
...
llvm-svn: 17074
2004-10-17 02:42:42 +00:00
29dc5f2a3e
Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly
...
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.
This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.
llvm-svn: 17068
2004-10-16 20:43:38 +00:00
fcfe78eaf8
Fix fix fix
...
llvm-svn: 17057
2004-10-16 18:21:50 +00:00
ea9a85abe4
Add support for undef and unreachable
...
llvm-svn: 17051
2004-10-16 18:14:10 +00:00
a3f3c8a1ad
ADd support for undef and unreachable
...
llvm-svn: 17050
2004-10-16 18:13:47 +00:00
e4bea062c7
Teach the X86 backend about unreachable and undef. Among other things, we
...
now compile:
'foo() {}' into "ret" instead of "mov EAX, 0; ret"
llvm-svn: 17049
2004-10-16 18:13:05 +00:00
583dfdcf86
Add support for unreachable and undef
...
llvm-svn: 17048
2004-10-16 18:12:13 +00:00
1a709646e7
Add a missing dependency
...
llvm-svn: 17031
2004-10-16 17:12:55 +00:00
947ecace14
Fix file header
...
llvm-svn: 17030
2004-10-16 16:37:42 +00:00
15914416ec
Instruction select globals with offsets better. For example, on this test
...
case:
int C[100];
int foo() {
return C[4];
}
We now codegen:
foo:
mov %EAX, DWORD PTR [C + 16]
ret
instead of:
foo:
mov %EAX, OFFSET C
mov %EAX, DWORD PTR [%EAX + 16]
ret
Other impressive features may be coming later.
This patch is contributed by Jeff Cohen!
llvm-svn: 17011
2004-10-15 05:05:29 +00:00
3b78938b9e
Give the X86 JIT the ability to encode global+disp constants. Patch
...
contributed by Jeff Cohen!
llvm-svn: 17010
2004-10-15 04:53:13 +00:00
19025d5ad0
Give the X86 asm printer the ability to print out addressing modes that have
...
constant displacements from global variables. Patch by Jeff Cohen!
llvm-svn: 17009
2004-10-15 04:44:53 +00:00
df7b984f5a
Allow X86 addressing modes to represent globals with offsets. Patch contributed
...
by Jeff Cohen!
llvm-svn: 17008
2004-10-15 04:43:20 +00:00
a15c246af9
Better codegen of binary integer ops with 32 bit immediate operands.
...
This transformation fires a few dozen times across the testsuite.
For example, int test2(int X) { return X ^ 0x0FF00FF0; }
Old:
_test2:
lis r2, 4080
ori r2, r2, 4080
xor r3, r3, r2
blr
New:
_test2:
xoris r3, r3, 4080
xori r3, r3, 4080
blr
llvm-svn: 17004
2004-10-15 00:50:19 +00:00
aa8f87c83c
The field is called `imm22', not simply `imm'
...
llvm-svn: 17003
2004-10-14 22:33:32 +00:00
b03f27c96c
Synthetic instructions RET and RETL need to have all 3 parameters specified
...
llvm-svn: 17002
2004-10-14 22:32:49 +00:00
b34fcdaa46
Class F2_1 already inherits the imm22 field from class F2
...
llvm-svn: 17001
2004-10-14 22:32:24 +00:00
7183fc3a84
Generate the SparcV8 code emitter from .td files
...
llvm-svn: 17000
2004-10-14 21:57:19 +00:00
98ebcd88f2
* In the F3_1 class, default asi to 0 because it's not currently used
...
* In the F3_3 class, remove mention of asi because it's not part of the format
llvm-svn: 16999
2004-10-14 21:53:39 +00:00
1f864b5583
Add FSTOI, FDTOI (fp to integer cast) instructions.
...
llvm-svn: 16996
2004-10-14 19:39:35 +00:00
1519c24cff
Rewrite emitCastOperation, refactoring parts of it into emitIntegerCast, and
...
adding emitFPToIntegerCast.
llvm-svn: 16995
2004-10-14 19:39:34 +00:00
38a4dd3d15
Add list of libc procedures we'll use, at some point.
...
Update list of currently failing tests.
ADJCALLSTACK* support is done.
llvm-svn: 16994
2004-10-14 19:39:33 +00:00
1f596c3358
* Claim to support machine code emission - return false from
...
addPassesToEmitMachineCode()
* Add support for registers and constants in getMachineOpValue()
This enables running "int main() { ret 0 }" via the PowerPC JIT.
llvm-svn: 16983
2004-10-14 06:39:56 +00:00
8b1bf4323f
* Include the real (generated) version of getBinaryCodeForInstr()
...
* Add implementation of getMachineOpValue() for generated code emitter
* Convert assert()s in unimplemented functions to abort()s so that non-debug
builds fail predictably
* Add file header comments
llvm-svn: 16981
2004-10-14 06:07:25 +00:00
c2d6aaeaa0
* Make a PPC32-specific code emitter because we have separate classes for 32-
...
and 64-bit code emitters that cannot share code unless we use virtual
functions
* Identify components being built by tablegen with more detail by assigning them
to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building
PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64
llvm-svn: 16980
2004-10-14 06:04:56 +00:00
d38a7605d8
Checking in code that works on my simple test case. However, there is still a bug with branches that I need to fix.
...
llvm-svn: 16979
2004-10-14 06:04:28 +00:00
189f3dc8d2
There is only one field in an instruction, and that is `Inst', the final view of
...
the instruction binary format, all others are simply operands and should not
have the `field' label
llvm-svn: 16978
2004-10-14 05:55:37 +00:00
d6ac8f5e5a
PowerPC instruction definitions use LittleEndian-style encoding [0..31]
...
llvm-svn: 16977
2004-10-14 05:54:38 +00:00
dba1f62eb8
Add isLittleEndianEncoding to InstrInfo class, defaults to `off'
...
llvm-svn: 16976
2004-10-14 05:53:40 +00:00
ace94df71f
Update to reflect changes in Makefile rules.
...
llvm-svn: 16950
2004-10-13 11:46:52 +00:00
58043a1473
Fix a warning that is emitted on the suns
...
llvm-svn: 16917
2004-10-11 15:50:40 +00:00
b4cb9fc7c9
Add ModuloScheduling to the recursive build tree
...
llvm-svn: 16905
2004-10-10 23:36:09 +00:00
9da1134bfb
Adjust header file inclusion due to move
...
llvm-svn: 16904
2004-10-10 23:34:50 +00:00
c70014bea3
Adjust comment header and paths to refect move
...
llvm-svn: 16903
2004-10-10 23:34:36 +00:00
4a4af7e20c
ModuloScheduling moved to lib/Target/SparcV9 as it is SparcV9-specific
...
llvm-svn: 16902
2004-10-10 23:33:20 +00:00
823f302ff9
Initial version of automake Makefile.am file.
...
llvm-svn: 16898
2004-10-10 22:52:14 +00:00
ef6ba8db70
Add the new InstrSched directory.
...
llvm-svn: 16897
2004-10-10 22:51:03 +00:00
97327f05fc
Initial version of automake Makefile.am file.
...
llvm-svn: 16893
2004-10-10 22:20:40 +00:00
4a69c9d667
Fix assertion failure when calling or returning from a function which
...
returns 'bool' type.
llvm-svn: 16884
2004-10-10 20:34:17 +00:00
7be91b34b8
Implement eliminateCallFramePseudoInstr().
...
Wrap a long comment line.
llvm-svn: 16883
2004-10-10 19:57:21 +00:00
9770e416c5
Model calls as *both* using *and* killing O0..O5, because callees use the
...
argument values passed in (so they're not dead until *after* the call),
and callees are free to modify those registers.
llvm-svn: 16882
2004-10-10 19:57:20 +00:00
8a4d5caa76
Fix whitespace and wrap some long lines.
...
Deal with allocating stack space for outgoing args and copying them into the
correct stack slots (at least, we can copy <=32-bit int args).
We now correctly generate ADJCALLSTACK* instructions.
llvm-svn: 16881
2004-10-10 19:57:18 +00:00
3acdb7fa1b
bling bling!
...
llvm-svn: 16873
2004-10-10 16:26:13 +00:00
f9ae6db749
Instead of silently breaking, print notification of why this doesn't work.
...
llvm-svn: 16870
2004-10-09 21:13:51 +00:00
74584cd842
update according to tonight's info
...
llvm-svn: 16866
2004-10-09 05:58:27 +00:00
9c0710781d
Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the
...
default 32/BE target on sparc hosts, and ppc will continue to be the default
on other hosts.
llvm-svn: 16865
2004-10-09 05:57:01 +00:00
23c8d0b65a
The person who was planning to add SSE support isn't anymore, so disable
...
the -sse* options (to avoid misleading people).
Also, the stack alignment of the target doesn't depend on whether SSE is
eventually implemented, so remove a comment.
llvm-svn: 16860
2004-10-08 22:41:46 +00:00
97ea4206f7
Fix a major regression from the bugfix for 2004-10-08-SelectSetCCFold.llx,
...
which prevented setcc's from being folded into branches. It appears that
conditional branchinst's CC operand is actually operand(2), not operand(0)
as we might expect. :(
llvm-svn: 16859
2004-10-08 22:24:31 +00:00
e4e1360eab
Adjust paths due to moving InstrSched to lib/Target/SparcV9
...
llvm-svn: 16852
2004-10-08 18:30:22 +00:00
24eb38af7c
InstrSched is SparcV9-specific and so has been moved to lib/Target/SparcV9/
...
llvm-svn: 16849
2004-10-08 18:12:14 +00:00
5a9976ac29
Single-space instead of double-spacing in the Makefile
...
llvm-svn: 16848
2004-10-08 18:11:14 +00:00
e75c26687c
Build InstrSched as well, and all three subdirs can be built independently
...
llvm-svn: 16847
2004-10-08 18:10:48 +00:00
0be2f50401
Fix bug: 2004-10-08-SelectSetCCFold.llx. Normally this is hidden by the
...
instcombine xform, which is why we didn't notice it before.
llvm-svn: 16840
2004-10-08 16:34:13 +00:00
b58dd6799f
Implement logical and with an immediate that consists of a contiguous block
...
of one or more 1 bits (may wrap from least significant bit to most
significant bit) as the rlwinm rather than andi., andis., or some longer
instructons sequence.
int andn4(int z) { return z & -4; }
int clearhi(int z) { return z & 0x0000FFFF; }
int clearlo(int z) { return z & 0xFFFF0000; }
int clearmid(int z) { return z & 0x00FFFF00; }
int clearwrap(int z) { return z & 0xFF0000FF; }
_andn4:
rlwinm r3, r3, 0, 0, 29
blr
_clearhi:
rlwinm r3, r3, 0, 16, 31
blr
_clearlo:
rlwinm r3, r3, 0, 0, 15
blr
_clearmid:
rlwinm r3, r3, 0, 8, 23
blr
_clearwrap:
rlwinm r3, r3, 0, 24, 7
blr
llvm-svn: 16832
2004-10-08 02:49:24 +00:00
6e6514c47e
Several fixes and enhancements to the PPC32 backend.
...
1. Fix an illegal argument to getClassB when deciding whether or not to
sign extend a byte load.
2. Initial addition of isLoad and isStore flags to the instruction .td file
for eventual use in a scheduler.
3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
that we can emit the PowerPC shifted immediate instructions far more
often. This allows us to emit the following code:
int foo(int x) { return x | 0x00F0000; }
_foo:
.LBB_foo_0: ; entry
; IMPLICIT_DEF
oris r3, r3, 15
blr
llvm-svn: 16826
2004-10-07 22:30:03 +00:00
c6b63cd2ed
Add ori reg, reg, 0 as a move instruction. This can be generated from
...
loading a 32bit constant into a register whose low halfword is all zeroes.
We now omit the ori after the lis for the following C code:
int bar(int y) { return y * 0x00F0000; }
_bar:
.LBB_bar_0: ; entry
; IMPLICIT_DEF
lis r2, 15
mullw r3, r3, r2
blr
llvm-svn: 16825
2004-10-07 22:26:12 +00:00
70a9d9c0b1
Remove unnecessary header include
...
llvm-svn: 16824
2004-10-07 22:24:32 +00:00
f94f985bbd
Correct some typeos
...
llvm-svn: 16770
2004-10-06 16:28:24 +00:00
93867e516a
Remove debugging code, fix encoding problem. This fixes the problems
...
the JIT had last night.
llvm-svn: 16766
2004-10-06 14:31:50 +00:00
9a1fbaf1e9
Turning on fsel code gen now that we can do so would be good.
...
llvm-svn: 16765
2004-10-06 11:03:30 +00:00
fac8529df8
Implement floating point select for lt, gt, le, ge using the powerpc fsel
...
instruction.
Now, rather than emitting the following loop out of bisect:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f4
bge .LBB_main_64 ; no_exit.0.i
.LBB_main_63: ; no_exit.0.i
b .LBB_main_65 ; no_exit.0.i
.LBB_main_64: ; no_exit.0.i
fmr f2, f1
.LBB_main_65: ; no_exit.0.i
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f1
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f5, lo16(.CPI_main_1-"L00000$pb")(r3)
fcmpu cr0, f1, f5
bge .LBB_main_67 ; no_exit.0.i
.LBB_main_66: ; no_exit.0.i
b .LBB_main_68 ; no_exit.0.i
.LBB_main_67: ; no_exit.0.i
fmr f4, f1
.LBB_main_68: ; no_exit.0.i
fadd f1, f2, f4
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fcmpu cr0, f4, f0
bgt .LBB_main_70 ; no_exit.0.i
.LBB_main_69: ; no_exit.0.i
b .LBB_main_71 ; no_exit.0.i
.LBB_main_70: ; no_exit.0.i
fmr f0, f4
.LBB_main_71: ; no_exit.0.i
fsub f1, f2, f1
addi r2, r2, -1
fcmpu cr0, f1, f3
blt .LBB_main_73 ; no_exit.0.i
.LBB_main_72: ; no_exit.0.i
b .LBB_main_74 ; no_exit.0.i
.LBB_main_73: ; no_exit.0.i
fmr f3, f1
.LBB_main_74: ; no_exit.0.i
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
We emit this instead:
.LBB_main_19: ; no_exit.0.i
rlwinm r3, r2, 3, 0, 28
lfdx f1, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f2, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f2, f2, f1
fsel f1, f1, f1, f2
addi r3, r2, 1
rlwinm r3, r3, 3, 0, 28
lfdx f2, r3, r27
addis r3, r30, ha16(.CPI_main_1-"L00000$pb")
lfd f4, lo16(.CPI_main_1-"L00000$pb")(r3)
fsub f4, f4, f2
fsel f2, f2, f2, f4
fadd f1, f1, f2
addis r3, r30, ha16(.CPI_main_2-"L00000$pb")
lfd f2, lo16(.CPI_main_2-"L00000$pb")(r3)
fmul f1, f1, f2
rlwinm r3, r2, 3, 0, 28
lfdx f2, r3, r28
fadd f4, f2, f1
fsub f5, f0, f4
fsel f0, f5, f0, f4
fsub f1, f2, f1
addi r2, r2, -1
fsub f2, f1, f3
fsel f3, f2, f3, f1
cmpwi cr0, r2, -1
fmr f16, f0
fmr f17, f3
bgt .LBB_main_19 ; no_exit.0.i
llvm-svn: 16764
2004-10-06 09:53:04 +00:00
6835dedb5b
Codegen signed mod by 2 or -2 more efficiently. Instead of generating:
...
t:
mov %EDX, DWORD PTR [%ESP + 4]
mov %ECX, 2
mov %EAX, %EDX
sar %EDX, 31
idiv %ECX
mov %EAX, %EDX
ret
Generate:
t:
mov %ECX, DWORD PTR [%ESP + 4]
*** mov %EAX, %ECX
cdq
and %ECX, 1
xor %ECX, %EDX
sub %ECX, %EDX
*** mov %EAX, %ECX
ret
Note that the two marked moves are redundant, and should be eliminated by the
register allocator, but aren't.
Compare this to GCC, which generates:
t:
mov %eax, DWORD PTR [%esp+4]
mov %edx, %eax
shr %edx, 31
lea %ecx, [%edx+%eax]
and %ecx, -2
sub %eax, %ecx
ret
or ICC 8.0, which generates:
t:
movl 4(%esp), %ecx #3.5
movl $-2147483647, %eax #3.25
imull %ecx #3.25
movl %ecx, %eax #3.25
sarl $31, %eax #3.25
addl %ecx, %edx #3.25
subl %edx, %eax #3.25
addl %eax, %eax #3.25
negl %eax #3.25
subl %eax, %ecx #3.25
movl %ecx, %eax #3.25
ret #3.25
We would be in great shape if not for the moves.
llvm-svn: 16763
2004-10-06 05:01:07 +00:00
e4c60eb704
Really fix FreeBSD, which apparently doesn't tolerate the extern.
...
Thanks to Jeff Cohen for pointing out my goof.
llvm-svn: 16762
2004-10-06 04:21:52 +00:00
7bd8f1332d
Fix a scary bug with signed division by a power of two. We used to generate:
...
s: ;; X / 4
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
sar %ECX, 1
shr %ECX, 30
mov %EDX, %EAX
add %EDX, %ECX
sar %EAX, 2
ret
When we really meant:
s:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, %EAX
sar %ECX, 1
shr %ECX, 30
add %EAX, %ECX
sar %EAX, 2
ret
Hey, this also reduces register pressure too :)
llvm-svn: 16761
2004-10-06 04:19:43 +00:00
147edd2f7e
Codegen signed divides by 2 and -2 more efficiently. In particular
...
instead of:
s: ;; X / 2
movl 4(%esp), %eax
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %edx
addl %ecx, %edx
sarl $1, %eax
ret
t: ;; X / -2
movl 4(%esp), %eax
movl %eax, %ecx
shrl $31, %ecx
movl %eax, %edx
addl %ecx, %edx
sarl $1, %eax
negl %eax
ret
Emit:
s:
movl 4(%esp), %eax
cmpl $-2147483648, %eax
sbbl $-1, %eax
sarl $1, %eax
ret
t:
movl 4(%esp), %eax
cmpl $-2147483648, %eax
sbbl $-1, %eax
sarl $1, %eax
negl %eax
ret
llvm-svn: 16760
2004-10-06 04:02:39 +00:00
e9bfa5a2a4
Add some new instructions. Fix the asm string for sbb32rr
...
llvm-svn: 16759
2004-10-06 04:01:02 +00:00
32ed828f46
FreeBSD uses GCC. Patch contributed by Jeff Cohen!
...
llvm-svn: 16756
2004-10-06 03:15:44 +00:00
d1ab378be5
* Prune #includes
...
* Update comments
* Rearrange code a bit
* Finally ELIMINATE the GAS workaround emitter for Intel mode. woot!
llvm-svn: 16647
2004-10-04 07:31:08 +00:00
68ab0beb1b
Add support for emitting AT&T style .s files, and make it the default. Users
...
may now choose their output format with the -x86-asm-syntax={intel|att} flag.
llvm-svn: 16646
2004-10-04 07:24:48 +00:00
8bbde2fb33
Convert some missed patterns to support AT&T style
...
llvm-svn: 16645
2004-10-04 07:23:07 +00:00
2e99778aad
Apparently the GNU assembler has a HUGE hack to be compatible with really
...
old and broken AT&T syntax assemblers. The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.
llvm-svn: 16644
2004-10-04 07:08:46 +00:00
af69503332
Fix incorrect suffix
...
llvm-svn: 16642
2004-10-04 05:20:16 +00:00
e1a2826d51
Fix some more missed suffixes and swapped operands
...
llvm-svn: 16641
2004-10-04 01:38:10 +00:00
a488f04f3e
Add missing suffixes to FP instructions for AT&T mode
...
llvm-svn: 16640
2004-10-04 00:43:31 +00:00
5683260187
Add support for the -x86-asm-syntax flag, which can be used to choose between
...
Intel and AT&T style assembly language. The ultimate goal of this is to
eliminate the GasBugWorkaroundEmitter class, but for now AT&T style emission
is not fully operational.
llvm-svn: 16639
2004-10-03 20:36:57 +00:00
4e59a14909
Add support to the instruction patterns for AT&T style output, which will
...
hopefully lead to the death of the 'GasBugWorkaroundEmitter'. This also
includes changes to wrap the whole file to 80 columns! Woot! :)
Note that the AT&T style output has not been tested at all.
llvm-svn: 16638
2004-10-03 20:35:00 +00:00
42c43b2cb3
Add initial support for variants
...
llvm-svn: 16635
2004-10-03 19:34:18 +00:00
dd9bb500ad
Make EmitMappingInfo into an "external location" option, so that it can be set
...
or cleared externally.
llvm-svn: 16623
2004-09-30 20:20:01 +00:00
a1640d2427
I think this will handle double args.
...
llvm-svn: 16618
2004-09-30 19:44:32 +00:00
7efd5fcb3a
Mark the instructions that have delay slots with the hasDelaySlot flag.
...
Add some comments.
llvm-svn: 16611
2004-09-30 04:04:48 +00:00
1f48ef2a9a
Use TargetMachine::hasDelaySlot() instead of our old switch statement
...
to find instrs that have delay slots.
llvm-svn: 16610
2004-09-30 04:04:47 +00:00
4592f86ef1
Change the #ifdefs to allow compilation with a V8 compiler, but the JIT still
...
won't work if not compiled in V9 mode, currently by GCC only, because Sun's
system compiler does not tell us if it's a V8 or V9 system.
llvm-svn: 16602
2004-09-29 23:01:17 +00:00
fb1fd0cb5f
Update list of shootout programs that should be working.
...
llvm-svn: 16595
2004-09-29 20:45:06 +00:00
ede068a8d3
Tell the target description that calls clobber registers O0...O5.
...
llvm-svn: 16594
2004-09-29 20:45:05 +00:00
3a340dd7cd
FITOD is spelled "fitod", not "fitos". Ouch.
...
llvm-svn: 16591
2004-09-29 19:59:07 +00:00
47095da661
Don't use .quad to output double constants. The assembler must have a bug or
...
something, because the wrong bit patterns get output.
llvm-svn: 16590
2004-09-29 19:59:06 +00:00
81f5e08573
Recognize FpMOVD as a move.
...
llvm-svn: 16586
2004-09-29 16:45:47 +00:00
2f1d0ae95e
Generate better code by being far less clever when it comes to the select instruction. Don't create overlapping register lifetimes
...
llvm-svn: 16580
2004-09-29 05:00:31 +00:00
c44da15813
add results
...
llvm-svn: 16579
2004-09-29 03:48:55 +00:00
7b6df6def2
improve Type::BoolTy codegen by eliminating unnecessary clears and sign extends
...
llvm-svn: 16578
2004-09-29 03:45:33 +00:00
4023d4e191
Simplify copyConstantToRegister() for longs, using a pair of recursive calls.
...
Copy constant-pool entries' addresses into registers before loading out of them,
to avoid errors from the assembler.
Handle loading call args past the 6th one off the stack.
Add IMPLICIT_DEF pseudo-instrs for double and long arguments passed in register
pairs.
Use FpMOVD to copy doubles around instead of the horrible store-load thing we
were doing before.
Handle 'ret double' and 'ret long'.
Fix a bug in handling 'and/or/xor long'.
llvm-svn: 16577
2004-09-29 03:34:41 +00:00
eae5b17dba
Fix bug recognizing moves: isMoveInstr should only treat ORs with %g0 as
...
moves, not all ORs.
llvm-svn: 16576
2004-09-29 03:28:15 +00:00
069bb989e4
Use FpMOVD pseudo-instruction to move doubles around.
...
llvm-svn: 16575
2004-09-29 03:27:30 +00:00
da371d9cf3
Add new FpMOVD pseudo-instruction, used to move doubles around.
...
llvm-svn: 16574
2004-09-29 03:27:29 +00:00
7f11dd4825
Fix double and long alignment.
...
Call the FPMover pass after register allocation.
llvm-svn: 16573
2004-09-29 03:26:27 +00:00
ead8e39832
Put quotes around argument to .section directive.
...
llvm-svn: 16572
2004-09-29 03:25:40 +00:00
457180c597
Add createSparcV8FPMoverPass().
...
llvm-svn: 16571
2004-09-29 03:25:39 +00:00
ce0ba4857b
Pass which converts FpMOVD (double move pseudoinstructions) to pairs
...
of FMOVS instrs.
llvm-svn: 16570
2004-09-29 03:24:34 +00:00
26566f0b68
To go along with sabre's improved InstCombining, improve recognition of
...
integers that we can use as immediate values in instructions.
Example from yacr2:
- lis r10, -1
- ori r10, r10, 65535
- add r28, r28, r10
+ addi r28, r28, -1
addi r7, r7, 1
addi r9, r9, 1
b .LBB_main_9 ; loopentry.1.i214
llvm-svn: 16566
2004-09-29 02:35:05 +00:00
c762ab723b
Add support for the isLoad and isStore flags, needed by the instruction scheduler
...
llvm-svn: 16555
2004-09-28 21:29:00 +00:00
6652223bd6
Capture delay slot info
...
llvm-svn: 16551
2004-09-28 18:34:14 +00:00
6280a7b716
Since we use alloca now make sure we include the proper headers for it.
...
llvm-svn: 16536
2004-09-28 02:53:15 +00:00
edbb20cf7f
Use alloca instead of a C99 style array. This should fix the
...
compilation problem in windows.
llvm-svn: 16535
2004-09-28 02:47:38 +00:00
3ce42ec7ee
Pull assignment out of for loop conditional in order for this to
...
compile under windows. Patch contributed by Paolo Invernizzi!
llvm-svn: 16534
2004-09-28 02:40:37 +00:00
d409d38151
SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!
...
llvm-svn: 16526
2004-09-27 18:22:18 +00:00
8656a156cf
Correct some BuildMI arguments for the upcoming simple scheduler
...
llvm-svn: 16519
2004-09-27 05:08:17 +00:00
a68d76ebfa
Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64.
...
llvm-svn: 16518
2004-09-26 21:07:43 +00:00
49cf74b26c
Fix the last of the major PPC GEP folding deficiencies. This will allow
...
the ISel to use indexed and non-zero immediate offsets for GEPs that have
more than one use. This is common for instruction sequences such as a load
followed by a modify and store to the same address.
llvm-svn: 16493
2004-09-23 05:31:33 +00:00
379a05b52a
Use the V8/V9 shared register file description
...
llvm-svn: 16485
2004-09-22 21:48:50 +00:00
3c08658d56
Combine the F2 and F3 instruction classes into one file for simplicity
...
llvm-svn: 16484
2004-09-22 21:38:42 +00:00
efce1ef9c3
Fix file header path
...
llvm-svn: 16483
2004-09-22 21:29:12 +00:00
009aaf9968
Prettify formatting of the file, adjust paths to making V8 a subdir of Sparc
...
llvm-svn: 16482
2004-09-22 20:09:29 +00:00
d55f854a5d
V8 is now a subdirectory of Sparc; adjust paths accordingly
...
llvm-svn: 16481
2004-09-22 20:08:52 +00:00
033b816171
add optimized code sequences for setcc x, 0
...
llvm-svn: 16478
2004-09-22 04:40:25 +00:00
89dd63733a
The real x87 floating point registers should not be allocatable. They
...
are only used by the stackifier when transforming FPn register
allocations to the real stack file x87 registers.
llvm-svn: 16472
2004-09-21 21:22:11 +00:00
6b17bf7193
s/ISel/PPC64ISel/ to have unique class names for debugging via gdb because the
...
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16471
2004-09-21 18:22:33 +00:00
87201ce8f9
s/ISel/PPC32ISel/ to have unique class names for debugging via gdb because the
...
C++ front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16470
2004-09-21 18:22:19 +00:00
43bd39e04e
s/ISel/X86ISel/ to have unique class names for debugging via gdb because the C++
...
front-end in gcc does not mangle classes in anonymous namespaces correctly.
llvm-svn: 16469
2004-09-21 18:21:21 +00:00
0f28cce60c
Make sure to set the operand list
...
llvm-svn: 16466
2004-09-21 17:30:54 +00:00
4f2cf030e8
'Pass' should now not be derived from by clients. Instead, they should derive
...
from ModulePass. Instead of implementing Pass::run, then should implement
ModulePass::runOnModule.
llvm-svn: 16436
2004-09-20 04:48:05 +00:00
6614946443
Convert code to compile with vc7.1.
...
Patch contributed by Paolo Invernizzi. Thanks Paolo!
llvm-svn: 16368
2004-09-15 17:06:42 +00:00
4bf01357e1
Fit long lines into 80 cols via creative space elimination
...
llvm-svn: 16353
2004-09-15 01:40:18 +00:00
2d01db846b
Targets are independent of each other, so compile them in parallel
...
llvm-svn: 16351
2004-09-15 01:34:25 +00:00
e8e81a2941
Revamp the Register class, and allow the use of the RegisterGroup class to
...
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
llvm-svn: 16330
2004-09-14 04:17:02 +00:00
247c29e4b0
Changes to make this work with Jason's patch. I checked this by hand, but
...
would appreciate if others would also look at this to make sure I didn't
botch something obvious
llvm-svn: 16312
2004-09-13 21:32:03 +00:00
72be9ae024
Fix filename: Printer.cpp has become X86AsmPrinter.cpp
...
llvm-svn: 16299
2004-09-12 21:26:04 +00:00
04bbe6fa25
Renamed file to SparcV8ISelSimple.cpp
...
llvm-svn: 16267
2004-09-10 18:51:12 +00:00
86584749b6
Roll back constant printing changes until the problems with larger
...
programs and C++ can be looked at in detail.
llvm-svn: 16266
2004-09-10 18:01:45 +00:00
371403193c
Use a shorter form to express implicit use/defs in FpGETRESULT and
...
FpSETRESULT.
llvm-svn: 16247
2004-09-08 18:29:31 +00:00
8b700215ed
A call instruction should implicitely define ST0 since the return
...
value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.
llvm-svn: 16246
2004-09-08 16:54:54 +00:00
acafb39cc3
This file does not need <iostream>, I think.
...
llvm-svn: 16245
2004-09-08 04:10:52 +00:00
54bcf2db01
Add 64 bit divide instructions, and use them
...
llvm-svn: 16198
2004-09-06 18:46:59 +00:00
175fdd4678
* Change PPC32AsmPrinter => PowerPCAsmPrinter since it is now shared between
...
Darwin and AIX and is not 32- or 64-bit specific
* Bring back PowerPC.td as a result, to make it use the `PowerPC' class name
* Adjust Makefile accordingly
llvm-svn: 16174
2004-09-05 02:42:44 +00:00
4acadb3af7
Renamed PPC32AsmPrinter.cpp => PowerPCAsmPrinter.cpp as the Darwin and AIX asm
...
printers are now unified into one file.
llvm-svn: 16173
2004-09-05 02:27:37 +00:00
4d847047a0
Include MathExtras.h to fix build breakage, thanks to Vladimir
...
llvm-svn: 16164
2004-09-04 14:51:26 +00:00
4bfceb1ed5
All PPC instructions are now auto-printed
...
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out
llvm-svn: 16163
2004-09-04 05:00:00 +00:00
0ded30aec4
Clean up some "clean:" targets so they use $(VERB) and don't print anything
...
by default, like every other "clean" target in LLVM.
llvm-svn: 16161
2004-09-03 23:19:53 +00:00
6173878304
Convert remaining X-Form and Pseudo instructions over to asm writer
...
llvm-svn: 16142
2004-09-02 08:13:00 +00:00
c6e81f0fde
Back to compiling land for v8
...
llvm-svn: 16138
2004-09-02 02:37:43 +00:00
7c16caa336
Changes For Bug 352
...
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.
llvm-svn: 16137
2004-09-01 22:55:40 +00:00
a113d74e4c
convert M and MD form instructions to generated asm writer
...
llvm-svn: 16121
2004-08-31 02:28:08 +00:00
143cf94f92
Move yet more instructions over to being printed by the generated asm writer
...
llvm-svn: 16112
2004-08-30 02:28:06 +00:00
8aca0b494d
Reduce the number of arguments in the instruction builder and make some
...
improvements on instruction selection that account for register and frame
index bases.
Patch contributed by Jeff Cohen. Thanks Jeff!
llvm-svn: 16110
2004-08-30 00:13:26 +00:00
6cdbd22245
Convert A-Form instructions to auto-generated asm writer
...
llvm-svn: 16107
2004-08-29 22:45:13 +00:00
434234f6d1
Register sizes should be specified in bits
...
llvm-svn: 16106
2004-08-29 22:03:40 +00:00
8cb6bd5f3c
Improvements to int->float cast code for PPC-64
...
llvm-svn: 16105
2004-08-29 22:02:43 +00:00
4483df8b63
Implement the following missing functionality in the PPC backend:
...
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite. Fixes Regression/casts
llvm-svn: 16081
2004-08-29 08:19:32 +00:00
fa2bf42539
Register sizes are in bits, not bytes
...
llvm-svn: 16070
2004-08-27 04:28:10 +00:00
8b5b3fdb50
Add getAllocatableSet() function.
...
llvm-svn: 16059
2004-08-26 22:21:04 +00:00
7f00753f70
Previous checkin broke printf(%a) support for fp constants-- re-fix it.
...
llvm-svn: 16051
2004-08-25 19:37:26 +00:00
35eb7aeae3
New version of Bill Wendling's PR33 patch.
...
llvm-svn: 16050
2004-08-25 19:00:42 +00:00
dfa9dbceaa
Add -sse[,2,3] arguments to LLC
...
llvm-svn: 16018
2004-08-24 08:18:44 +00:00
61e6dbc761
Nuke commented out stuff
...
llvm-svn: 16017
2004-08-24 08:18:27 +00:00
75dca84c7f
This code is dodgy, but the guaranteed assertion failure doesn't help anything.
...
llvm-svn: 16014
2004-08-24 06:41:40 +00:00
98aa7797c3
Fix bug in PhyRegAlloc::setCallInterferences() handling call through a
...
null pointer.
llvm-svn: 16013
2004-08-24 06:41:39 +00:00
d315f43587
Revise head-of-file comment.
...
Eliminate some excess whitespace.
Fix bug in CallArgsDescriptor::get() handling call through a null pointer.
llvm-svn: 16012
2004-08-24 06:41:38 +00:00
1c57b4fa32
Kill a majority of unnecessary sign extensions for byte loads
...
llvm-svn: 15991
2004-08-22 08:10:15 +00:00
64ef0262bd
Don't hard code the offset of the saved R31 in functions with frame pointers
...
llvm-svn: 15990
2004-08-22 08:09:17 +00:00
Brian Gaeke