Commit Graph

290315 Commits

Author SHA1 Message Date
Petr Hosek f6dda7cb44 [CMake] Use a different source depending on C++ support
When using system C++ library, assume we have a working C++ compiler and
try to compile a complete C++ program. When using in tree C++ library,
only check the C compiler since the C++ library likely won't have been
built yet at time of running the check.

Differential Revision: https://reviews.llvm.org/D47169

llvm-svn: 332924
2018-05-22 01:01:56 +00:00
Petr Hosek 0681d9e6d9 [CMake] Pass Clang defaults to runtimes builds
This enables the use of Clang default options from runtimes CMake files.

Differential Revision: https://reviews.llvm.org/D47168

llvm-svn: 332923
2018-05-22 00:43:04 +00:00
Jim Ingham a435d73349 Work around some odd instruction single-step behavior on macOS.
We've seen some cases on macOS where you go to instruction single
step (over a breakpoint), and single step returns but the instruction
hasn't been executed (and the pc hasn't moved.)  The ThreadPlanStepOverBreakpoint
used to handle this case by accident, but the patches to handle two adjacent
breakpoints broke that accident.

This patch fixes the logic of ExplainsStop to explicitly handle the case where
the pc didn't move.  It also adds a WillPop that re-enables the breakpoint we
were stepping over.  We never want an unexpected path through the plan to
fool us into not doing that.

I have no idea how to make this bug happen.  It is very inconsistent when it
occurs IRL.  We really need a full MockProcess Plugin before we can start to write
tests for this sort of system hiccup.

<rdar://problem/38505726>

llvm-svn: 332922
2018-05-22 00:06:55 +00:00
Sanjay Patel 17a870f07c [DAG] fold FP binops with undef operands to NaN
This is the FP sibling of D43141 with the corresponding IR change in rL327212.

We can't propagate undef here because if a variable operand is a NaN, these 
binops must propagate NaN. Neither global nor node-level fast-math makes a 
difference. If we have 'nnan', I think later folds can turn the NaN into undef.

The tests in X86/fp-undef.ll are meant to be the definitive verification for 
these folds - everything reduces identically now.

The other test changes are collateral damage. They may need to be altered to
preserve their intent.

Differential Revision: https://reviews.llvm.org/D47026

llvm-svn: 332920
2018-05-21 23:54:19 +00:00
Lang Hames 5cb2e30c98 [ORC] Make some more operations on VSO private. These should be done via a
MaterializationResponsibility instance.

llvm-svn: 332919
2018-05-21 23:46:29 +00:00
Lang Hames 373f4628a5 [LKH] Add a replacement RTDyldLayer.
llvm-svn: 332918
2018-05-21 23:45:40 +00:00
Roman Tereshin f1aa348b31 Reapply r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..."
Apparently the compile time problem was caused by the fact that not
all compilers / STL implementations can automatically convert
std::unique_ptr<Derived> to std::unique_ptr<Base>. Fixed (hopefully)
by making sure it's std::unique_ptr<Derived>&& (rvalue ref) to
std::unique_ptr<Base> conversion instead.

llvm-svn: 332917
2018-05-21 23:28:51 +00:00
Craig Topper 358b094971 [X86] Remove 128/256-bit cvtdq2ps, cvtudq2ps, cvtqq2pd, cvtuqq2pd intrinsics.
These can all be implemented with sitofp/uitofp instructions.

llvm-svn: 332916
2018-05-21 23:15:00 +00:00
Paul Semel 040df77ed6 [llvm-objcopy] Add --strip-unneeded option
This option removes symbols that are not needed by relocations.

Differential Revision: https://reviews.llvm.org/D46896

llvm-svn: 332915
2018-05-21 22:50:32 +00:00
Jim Ingham 99f7011829 Fix the Xcode project for the refactoring of the
DWARF reader.

llvm-svn: 332914
2018-05-21 22:41:28 +00:00
Raphael Isemann 456d43b98b Add missing include for cstdint to Visibility.h
Summary: We use uint8_t in this header, so we need to include cstdint.

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D47164

llvm-svn: 332913
2018-05-21 22:27:22 +00:00
Roman Tereshin 8bdf7be5bb Revert r332907 "[GlobalISel] Improving InstructionSelect's performance by reducing MatchTable..."
There is a compile time error I didn't see locally, investigating now.

llvm-svn: 332912
2018-05-21 22:21:24 +00:00
Peter Collingbourne ed05e2336d Add missing x86-registered-target.
llvm-svn: 332911
2018-05-21 22:14:02 +00:00
Diego Caballero 1bd5f2261d Fix warning from r332654 with LLVM_ATTRIBUTE_USED
r332654 tried to fix an unused function warning with
a void cast. This approach worked for clang and gcc 
but not for MSVC. This commit replaces the void cast
with the LLVM_ATTRIBUTE_USED approach.

llvm-svn: 332910
2018-05-21 22:12:38 +00:00
Craig Topper 9efb77e25f [X86] Remove a builtin that should have been removed in r332882.
llvm-svn: 332909
2018-05-21 22:10:02 +00:00
Peter Collingbourne 7de496f460 Unbreak kaleidoscope example.
llvm-svn: 332908
2018-05-21 22:09:45 +00:00
Roman Tereshin f0dc9fa934 [GlobalISel] Improving InstructionSelect's performance by reducing MatchTable, mostly NFC, perf patch 1
This patch starts a series of patches that decrease time spent by
GlobalISel in its InstructionSelect pass by roughly 60% for -O0 builds
for large inputs as measured on sqlite3-amalgamation
(http://sqlite.org/download.html) targeting AArch64.

The performance improvements are achieved solely by reducing the
number of matching GIM_* opcodes executed by the MatchTable's
interpreter during the selection by approx. a factor of 30, which also
brings contribution of this particular part of the selection process
to the overall runtime of InstructionSelect pass down from approx.
60-70% to 5-7%, thus making further improvements in this particular
direction not very profitable.

The improvements described above are expected for any target that
doesn't have many complex patterns. The targets that do should
strictly benefit from the changes, but by how much exactly is hard to
estimate beforehand. It's also likely that such target WILL benefit
from further improvements to MatchTable, most likely the ones that
bring it closer to a perfect decision tree.

This commit specifically is rather large mostly NFC commit that does
necessary preparation work and refactoring, there will be a following
series of small patches introducing a specific optimization each
shortly after.

This commit specifically is expected to cause a small compile time
regression (around 2.5% of InstructionSelect pass time), which should
be fixed by the next commit of the series.

Every commit planned shares the same Phabricator Review.

Reviewers: qcolombet, dsanders, bogner, aemerson, javed.absar

Reviewed By: qcolombet

Subscribers: rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D44700

llvm-svn: 332907
2018-05-21 22:04:39 +00:00
Peter Collingbourne 0322e3cbf5 Fix another make_unique ambiguity.
llvm-svn: 332906
2018-05-21 21:48:17 +00:00
Roman Lebedev 9f65d16d5d [DAGCombiner] isAllOnesConstantOrAllOnesSplatConstant(): look through bitcasts
Summary:
As pointed out in D46528, we errneously transform cases like `xor X, -1`,
even though we use said function.
It's because the `-1` is actually a bitcast there.
So i think we can just look through it in the function.

Differential Revision: https://reviews.llvm.org/D47156

llvm-svn: 332905
2018-05-21 21:41:10 +00:00
Roman Lebedev 7772de25d0 [DAGCombine][X86][AArch64] Masked merge unfolding: vector edition.
Summary:
This **appears** to be the last missing piece for the masked merge pattern handling in the backend.

This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]].

[[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly.
Previously, `andps`+`andnps` / `bsl` would be generated. (see `@out`)
Now, they would no longer be generated  (see `@in`), and we need to make sure that they are generated.

Differential Revision: https://reviews.llvm.org/D46528

llvm-svn: 332904
2018-05-21 21:41:02 +00:00
Roman Lebedev fd79bc3aa2 [X86][AArch64][NFC] Add tests for vector masked merge unfolding
Summary:
This is [[ https://bugs.llvm.org/show_bug.cgi?id=37104 | PR37104 ]].

[[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] will introduce an IR canonicalization that is likely bad for the end assembly.
Previously, `andps`+`andnps` / `bsl` would be generated. (see `@out`)
Now, they would no longer be generated  (see `@in`).

Differential Revision: https://reviews.llvm.org/D46008

llvm-svn: 332903
2018-05-21 21:40:51 +00:00
Marshall Clow df8f754792 Implement deduction guides for vector
llvm-svn: 332901
2018-05-21 21:30:12 +00:00
Lang Hames 502f81e37e [ORC] Preserve Materializing symbol flag during resolution.
llvm-svn: 332899
2018-05-21 21:11:22 +00:00
Lang Hames 0b0b41fcce [ORC] Lookup now returns an error if any symbols are not found.
Also tightens the behavior of ExecutionSession::failQuery. Queries can usually
only be failed by marking a symbol as failed-to-materialize, but
ExecutionSession::failQuery provides a second route, and both routes may be
executed from different threads. In the case that a query has already been
failed due to a materialization error, ExecutionSession::failQuery will
direct the error to ExecutionSession::reportError instead.

llvm-svn: 332898
2018-05-21 21:11:21 +00:00
Lang Hames add9b6805c [ORC] Remove the optional MaterializationResponsibility argument from lookup.
The lookup function provides blocking symbol resolution for JIT clients (not
layers themselves) so it does not need to track symbol dependencies via a
MaterializationResponsibility.

llvm-svn: 332897
2018-05-21 21:11:21 +00:00
Lang Hames 1cf9987f6e [ORC] Add IRLayer and ObjectLayer interfaces and related MaterializationUnits.
llvm-svn: 332896
2018-05-21 21:11:13 +00:00
Craig Topper 25444c852a [DAGCombiner] Use computeKnownBits to match rotate patterns that have had their amount masking modified by simplifyDemandedBits
SimplifyDemandedBits can remove bits from the masks for the shift amounts we need to see to detect rotates.

This patch uses zeroes from computeKnownBits to fill in some of these mask bits to make the match work.

As currently written this calls computeKnownBits even when the mask hasn't been simplified because it made the code simpler. If we're worried about compile time performance we can improve this.

I know we're talking about making a rotate intrinsic, but hopefully we can go ahead and do this change and just make sure the rotate intrinsic also handles it.

Differential Revision: https://reviews.llvm.org/D47116

llvm-svn: 332895
2018-05-21 21:09:18 +00:00
Sanjay Patel ec50effbd6 [InstCombine] regenerate checks; NFC
llvm-svn: 332894
2018-05-21 21:09:14 +00:00
Reid Kleckner 537917d13c [X86] Simplify some X86 address mode folding code, NFCI
This code should really do exactly the same thing for 32-bit x86 and
64-bit small code models, with the exception that RIP-relative
addressing can't use base and index registers.

llvm-svn: 332893
2018-05-21 21:03:19 +00:00
Craig Topper dc3bf90447 [X86] Remove some unneeded check lines that I copy and pasted when I made vector tests from some scalar test cases.
llvm-svn: 332892
2018-05-21 21:01:13 +00:00
Craig Topper 288bd2e5a0 [X86] Remove masking from pternlog llvm intrinsics and use a select instruction instead.
Because the intrinsics in the headers are implemented as macros, we can't just use a select builtin and pternlog builtin. This would require one of the macro arguments to be used twice. Depending on what was passed to the macro we could expand an expression twice leading to weird behavior. We could maybe declare our local variable in the macro, but that would need to worry about name collisions.

To avoid that just generate IR directly in CGBuiltin.cpp.

Differential Revision: https://reviews.llvm.org/D47125

llvm-svn: 332891
2018-05-21 20:58:23 +00:00
Craig Topper aad3aefaeb [X86] Remove masking from vpternlog intrinsics. Use a select in IR instead.
This removes 6 intrinsics since we no longer need separate mask and maskz intrinsics.

Differential Revision: https://reviews.llvm.org/D47124

llvm-svn: 332890
2018-05-21 20:58:09 +00:00
Peter Collingbourne 274c4f7ab4 Fix a make_unique ambiguity.
llvm-svn: 332889
2018-05-21 20:56:28 +00:00
Walter Lee ead3b3487b [asan] Make GetCurrentThread RTEMS-friendly
On RTEMS, system and user code all live in a single binary and address
space. There is no clean separation, and instrumented code may
execute before the ASan run-time is initialized (or after it has been
destroyed).

Currently, GetCurrentThread() may crash if it's called before ASan
run-time is initialized. Make it return nullptr instead.

Similarly, fix __asan_handle_no_return so that it gives up rather than
try something that may crash.

Differential Revision: https://reviews.llvm.org/D46459

llvm-svn: 332888
2018-05-21 20:43:36 +00:00
Sanjay Patel b8346e3f07 [InstCombine] remove fptrunc (select) code; NFCI
This pattern is handled within commonCastTransforms(),
so the code here is dead AFAICT.

llvm-svn: 332887
2018-05-21 20:39:35 +00:00
Richard Smith 3f1d6de4f7 Revert r332847; it caused us to miscompile certain forms of reference initialization.
llvm-svn: 332886
2018-05-21 20:36:58 +00:00
Peter Collingbourne 47bc01786d CodeGen, Driver: Start using direct split dwarf emission in clang.
Fixes PR37466.

Differential Revision: https://reviews.llvm.org/D47093

llvm-svn: 332885
2018-05-21 20:31:59 +00:00
Peter Collingbourne c5a9765cea LTO: Replace split dwarf implementation that uses objcopy with one that uses direct emission.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47091

llvm-svn: 332884
2018-05-21 20:26:49 +00:00
Sanjay Patel 94b1f846b2 [InstCombine] add tests for cast-of-select; NFC
In all cases, we're pulling the cast above the select.
That's not a good canonicalization if we're creating 
a select that then mismatches the operand size of its
condition.

llvm-svn: 332883
2018-05-21 20:23:58 +00:00
Craig Topper 842171de36 [X86] Use __builtin_convertvector to implement some of the packed integer to packed float conversion intrinsics.
I believe this is safe assuming default default FP environment. The conversion might be inexact, but it can never overflow the FP type so this shouldn't be undefined behavior for the uitofp/sitofp instructions.

We already do something similar for scalar conversions.

Differential Revision: https://reviews.llvm.org/D46863

llvm-svn: 332882
2018-05-21 20:19:17 +00:00
Peter Collingbourne 9a45114b3c CodeGen: Add a dwo output file argument to addPassesToEmitFile and hook it up to dwo output.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47089

llvm-svn: 332881
2018-05-21 20:16:41 +00:00
Reid Kleckner 9b2df56c59 Remove CMake workaround for LLD PR24476 which is no longer needed
llvm-svn: 332880
2018-05-21 20:14:46 +00:00
Richard Smith bbb2655de0 Revert r332028; see PR37545 for details.
llvm-svn: 332879
2018-05-21 20:10:54 +00:00
Brian Gesiak a398590f56 [DebugInfo] Fix typo "DWARG" in test comment (NFC)
Summary:
The correct spelling is "DWARF", the debugging format, not "DWARG".
The typo is in a (not executed by lit) comment in a test file, so
fixing it does not result in any functional change.

Test Plan: check-llvm, just in case

llvm-svn: 332878
2018-05-21 19:48:27 +00:00
Zachary Turner f36b128bae Enable Python API for OpenBSD.
Patch by David Carlier

llvm-svn: 332877
2018-05-21 19:47:45 +00:00
Kostya Serebryany 69c2b71a51 [libFuzzer] reinstate -dump_coverage, which is still in use (reverts r332036)
llvm-svn: 332876
2018-05-21 19:47:00 +00:00
Peter Collingbourne 63062d9d0f MC: Introduce an ELF dwo object writer and teach llvm-mc about it.
Part of PR37466.

Differential Revision: https://reviews.llvm.org/D47051

llvm-svn: 332875
2018-05-21 19:44:54 +00:00
Matt Arsenault 16fcc5b6db AMDGPU: Update GCCBuiltin names for DS FP atomic intrinsics
llvm-svn: 332874
2018-05-21 19:43:02 +00:00
Jonas Devlieghere c111382aa8 [DebugInfo] Use absolute addresses in location lists
Rather than relying on the user to do the address calculating in
DW_AT_location we should just dump the absolute address.

rdar://problem/38513870

Differential revision: https://reviews.llvm.org/D47152

llvm-svn: 332873
2018-05-21 19:36:54 +00:00
Craig Topper a010b3c9dc [X86] Add test cases for D47012.
Patch by Thomasz Krupa.

llvm-svn: 332872
2018-05-21 19:33:42 +00:00