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11447 Commits

Author SHA1 Message Date
Dan Gohman c16d9afe04 Add a basic testcase for TBAA-aware DSE. 
llvm-svn: 117632
 2010-10-29 00:54:02 +00:00
Chris Lattner 5d6f6a061b add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Andrew Trick fc1b990b1d The ARM jit cannot handle these tests as of 2010-10-27. 
(A PR will be linked to this rev.)

llvm-svn: 117620
 2010-10-29 00:23:43 +00:00
Rafael Espindola 8aefb66376 Improvements to .section parsing: 
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G

We ignore the G arguments and flag for now.

llvm-svn: 117608
 2010-10-28 21:33:33 +00:00
Chris Lattner 327a61423b most simple arm instructions match correctly now, 
it looks like we're not handling [] operands though

llvm-svn: 117607
 2010-10-28 21:31:07 +00:00
Chris Lattner 1be0697ab9 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Rafael Espindola 63760ba38e Add support for the .string directive. 
llvm-svn: 117592
 2010-10-28 20:02:27 +00:00
Rafael Espindola 3c5a54e4b9 Defined weak symbols should have non-zero value. 
llvm-svn: 117585
 2010-10-28 19:39:57 +00:00
Rafael Espindola 29f70afbae Fix relocations with renamed symbols. 
llvm-svn: 117575
 2010-10-28 19:08:03 +00:00
Rafael Espindola 6cd76e63f8 Aliases defined with .symver should copy the binding of the symbols they alias. 
Move the existing patching for undefined symbols so that all the patching
is done in the same function.

llvm-svn: 117570
 2010-10-28 18:33:03 +00:00
Bob Wilson f63da12be9 Teach the DAG combiner to fold a splat of a splat. Radar 8597790. 
Also do some minor refactoring to reduce indentation.

llvm-svn: 117558
 2010-10-28 17:06:14 +00:00
Roman Divacky fdac6365ab Implement .equ directive as a synonym to .set. 
llvm-svn: 117553
 2010-10-28 16:22:58 +00:00
Duncan Sands efb139130f Testcase for PR8494 (invalid bitcode crashing the bitcode reader). 
llvm-svn: 117552
 2010-10-28 15:57:30 +00:00
Rafael Espindola 936ba3af28 Implement R_X86_64_DTPOFF32. 
llvm-svn: 117548
 2010-10-28 15:11:03 +00:00
Rafael Espindola 2dbec3f762 Implement TLSLD. 
llvm-svn: 117547
 2010-10-28 15:02:40 +00:00
Rafael Espindola e8f08be11c Implement DTPOFF. 
llvm-svn: 117546
 2010-10-28 14:48:59 +00:00
Rafael Espindola 6f23eb380d Implement TLSLDM. 
llvm-svn: 117544
 2010-10-28 14:37:09 +00:00
Rafael Espindola b3b49bbc39 Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind. 
llvm-svn: 117543
 2010-10-28 14:22:44 +00:00
Evan Cheng ff310737e5 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng 0165e25564 Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful. 
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530
 2010-10-28 06:46:17 +00:00
NAKAMURA Takumi 959807fa37 test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack of nearbyintf on MSVC. [PR8466] 
llvm-svn: 117529
 2010-10-28 06:46:04 +00:00
Evan Cheng e2c211c1b9 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng ff1c862f8e - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Dale Johannesen 9c3f6bf2bf Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Owen Anderson 2ef668840a Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson 14be930317 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Dale Johannesen 16bb87a90e Teach InstCombine not to use Add and Neg on FP. PR 8490. 
llvm-svn: 117510
 2010-10-27 23:45:18 +00:00
Evan Cheng 59bbc545e0 Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Owen Anderson 9f371e7efa Tests for NEON encoding of vrev. 
llvm-svn: 117502
 2010-10-27 22:54:49 +00:00
Owen Anderson fadb951e5b Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Owen Anderson ed9652f959 Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Rafael Espindola f8537165bd Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE. 
llvm-svn: 117494
 2010-10-27 21:23:52 +00:00
Kevin Enderby 5e7cb5fc27 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Bob Wilson c7334a146e SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Rafael Espindola 24c8b04d5f Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32. 
llvm-svn: 117481
 2010-10-27 20:28:07 +00:00
Owen Anderson 40d24a4abf Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Rafael Espindola 095fa9e5cc Set default type and flags for .init and .fini. 
llvm-svn: 117471
 2010-10-27 18:45:20 +00:00
Owen Anderson fbdeab911a Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun. 
llvm-svn: 117469
 2010-10-27 18:17:12 +00:00
Owen Anderson 5fa98baef7 Tests for NEON encoding of vcls, vclz, and vcnt. 
llvm-svn: 117466
 2010-10-27 18:05:25 +00:00
Owen Anderson 6b5af599c0 Tests for NEON encoding of vneg and vqneg. 
llvm-svn: 117463
 2010-10-27 17:57:26 +00:00
Rafael Espindola 26496e6835 Produce an error for an invalid use of .symver. 
llvm-svn: 117462
 2010-10-27 17:56:18 +00:00
Owen Anderson 1e5eb98ed8 Tests for NEON encoding of vabs and vqabs. 
llvm-svn: 117460
 2010-10-27 17:50:07 +00:00
Owen Anderson 8576a42cf3 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson d7e8135e1e Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Rafael Espindola cc1b168ef6 Symbols defined as the difference of other two end up in the ABS section. 
llvm-svn: 117451
 2010-10-27 16:04:30 +00:00
Rafael Espindola eb0c2c170d Add support for the .symver directive. This is really ugly, but most of it is 
contained in the ELF object writer.

llvm-svn: 117448
 2010-10-27 15:18:17 +00:00
Kevin Enderby 9ad2166899 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby 20b021c970 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby a1917c7555 Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Kevin Enderby ba985d9dd5 Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Owen Anderson 825b2d1946 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Owen Anderson 2888e2c7f9 Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Jim Grosbach 3fe94f1e9f FileCheck'ize 
llvm-svn: 117401
 2010-10-26 21:26:47 +00:00
Owen Anderson c4126a1a2c Add tests for NEON encoding of vshll. 
llvm-svn: 117399
 2010-10-26 21:21:47 +00:00
Owen Anderson 0fbb20769f Tests for NEON encoding of vshr. 
llvm-svn: 117396
 2010-10-26 21:08:42 +00:00
Owen Anderson 3665fee8de Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Rafael Espindola c9fb35e73b Add support for .ident. 
llvm-svn: 117389
 2010-10-26 19:35:47 +00:00
Owen Anderson db192ba90f Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts. 
llvm-svn: 117385
 2010-10-26 18:43:13 +00:00
Owen Anderson b3bcf529fc Tests for NEON encodings of vpmin and vpmax. 
llvm-svn: 117382
 2010-10-26 18:31:47 +00:00
Owen Anderson 691ce68d3c Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Owen Anderson 035b3261ee Tests for NEON encoding of vpadd and vpaddl. 
llvm-svn: 117377
 2010-10-26 18:04:51 +00:00
Owen Anderson 284cb361d1 Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Rafael Espindola e8ae98817a Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
 2010-10-26 14:09:12 +00:00
Kalle Raiskila a49d062234 Change v64 datalayout in SPU. 
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.

llvm-svn: 117360
 2010-10-26 10:45:47 +00:00
Bob Wilson e1961fe289 When the "true" and "false" blocks of a diamond if-conversion are the same, 
do not double-count the duplicate instructions by counting once from the
beginning and again from the end.  Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end.  Radar 8589805.

This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction.  That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.

llvm-svn: 117333
 2010-10-26 00:02:24 +00:00
Owen Anderson c0f777afbf Tests for NEON encoding of vmax. 
llvm-svn: 117327
 2010-10-25 23:45:34 +00:00
Owen Anderson 144c3f8c6a Tests for NEON encoding of vmin. 
llvm-svn: 117326
 2010-10-25 23:35:36 +00:00
Dale Johannesen ec57ac1c3c An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.

llvm-svn: 117322
 2010-10-25 22:17:05 +00:00
Owen Anderson 1f6aad053d Add correct encodings for NEON vabal. 
llvm-svn: 117315
 2010-10-25 21:29:04 +00:00
Owen Anderson b9c91679aa Add correct NEON encodings for vaba. 
llvm-svn: 117309
 2010-10-25 20:52:57 +00:00
Owen Anderson 12214ddaa3 Tests for NEON encoding of vabdl. 
llvm-svn: 117303
 2010-10-25 20:36:28 +00:00
Owen Anderson 64aa05f865 Add tests for NEON encoding of vabd. 
llvm-svn: 117302
 2010-10-25 20:29:27 +00:00
Daniel Dunbar b3a48f3459 MC/AsmParser: Fix relative precedence of {+,-} and comparison ops. 
llvm-svn: 117299
 2010-10-25 20:18:56 +00:00
Daniel Dunbar 7484d2cbec MC/AsmLexer: Fix bug in source location for Slash token. 
llvm-svn: 117298
 2010-10-25 20:18:53 +00:00
Daniel Dunbar 95db1cc022 tweak test. 
llvm-svn: 117297
 2010-10-25 20:18:49 +00:00
Daniel Dunbar 0c193ca626 MC/AsmParser: Rewrite test to actually check some parts of expression parsing, 
now that we have macros and friends. Uncovered a bug in macro expansion...

llvm-svn: 117295
 2010-10-25 20:18:41 +00:00
Owen Anderson dd001b89d7 Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
llvm-svn: 117294
 2010-10-25 20:17:22 +00:00
Owen Anderson dea09c7564 Provide correct NEON encodings for vbsl. 
llvm-svn: 117293
 2010-10-25 20:13:13 +00:00
Owen Anderson 2477446ee5 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Owen Anderson dff239c5f9 Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Owen Anderson d9cdda9ddc Add tests for NEON encoding of vtst. 
llvm-svn: 117277
 2010-10-25 18:10:34 +00:00
Owen Anderson feb3ee0c93 Add NEON encoding tests for vcgt and vacgt. 
llvm-svn: 117276
 2010-10-25 18:03:59 +00:00
Rafael Espindola 0ed1543d4e Add support for emitting ARM file attributes. 
llvm-svn: 117275
 2010-10-25 17:50:35 +00:00
Owen Anderson e5d0677173 Add tests for NEON encodings of vcge and vacge. 
llvm-svn: 117274
 2010-10-25 17:49:32 +00:00
Owen Anderson c178b80f65 Add a warning about our inability to test the encoding of vceq with immediate zero. 
llvm-svn: 117273
 2010-10-25 17:33:02 +00:00
Owen Anderson 02917f5b1b Add tests for NEON encoding of vceq. 
llvm-svn: 117270
 2010-10-25 17:20:26 +00:00
Owen Anderson a9ad6c0645 Add tests for NEON encoding of vsubhn and vrsubhn. 
llvm-svn: 117269
 2010-10-25 17:12:46 +00:00
Dan Gohman 2e20dfb0f2 Fix a case where instcombine was stripping metadata (and alignment) 
from stores when folding in bitcasts.

llvm-svn: 117265
 2010-10-25 16:16:27 +00:00
Duncan Sands 31c803b2ba Fix PR8445: a block with no predecessors may be the entry block, in which case 
it isn't unreachable and should not be zapped.  The check for the entry block
was missing in one case: a block containing a unwind instruction.  While there,
do some small cleanups: "M" is not a great name for a Function* (it would be
more appropriate for a Module*), change it to "Fn"; use Fn in more places.

llvm-svn: 117224
 2010-10-24 12:23:30 +00:00
Owen Anderson 358900d569 Add tests for NEON encoding of vqsub. 
llvm-svn: 117214
 2010-10-23 18:02:16 +00:00
Michael J. Spencer aa19ee17c0 X86: Emit _fltused instead of __fltused on Windows x64. 
llvm-svn: 117205
 2010-10-23 09:06:59 +00:00
Mikhail Glushenkov f4a6809231 Remove -llvmc-temp-hack from tblgen. 
llvm-svn: 117197
 2010-10-23 07:32:53 +00:00
Owen Anderson 92644efaf8 Add tests for NEON encoding of vhsub. 
llvm-svn: 117189
 2010-10-22 23:58:22 +00:00
Jim Grosbach 0ce06c08fb Add a CMP test. 
llvm-svn: 117187
 2010-10-22 23:48:01 +00:00
Owen Anderson f4e1a09d38 Add tests for NEON encoding of vsubw. 
llvm-svn: 117186
 2010-10-22 23:46:07 +00:00
Jim Grosbach 4663dc72e2 tidy up 
llvm-svn: 117185
 2010-10-22 23:46:04 +00:00
Owen Anderson 9ef5c507ce Add tests for NEON encoding of vsubl. 
llvm-svn: 117183
 2010-10-22 23:36:36 +00:00
Owen Anderson c372775cc8 Add tests for NEON encoding of vsub. 
llvm-svn: 117177
 2010-10-22 23:21:04 +00:00
Owen Anderson cb5c1b75fe Add tests for NEON encoding of vqdmlsl. 
llvm-svn: 117173
 2010-10-22 23:08:47 +00:00
Owen Anderson d655a80774 Add tests for NEON encoding of vmlsl. 
llvm-svn: 117171
 2010-10-22 23:02:27 +00:00
Jim Grosbach b40a60fa2f tidy up. 
llvm-svn: 117166
 2010-10-22 22:15:48 +00:00
Jim Grosbach 2c9ae05c67 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Jim Grosbach 3565b0a2e2 Remove duplicate test. 
llvm-svn: 117158
 2010-10-22 22:04:28 +00:00
Jim Grosbach 6d993fa1a6 tidy up. 
llvm-svn: 117157
 2010-10-22 22:01:56 +00:00
Jim Grosbach db7415075d FileCheck-ize a few tests. 
llvm-svn: 117156
 2010-10-22 21:55:03 +00:00
Bob Wilson a4e231c880 Teach instcombine to set the alignment arguments for NEON load/store intrinsics. 
llvm-svn: 117154
 2010-10-22 21:41:48 +00:00
Owen Anderson 3c4f72c9f8 Add tests for the correct encoding of NEON vmls. 
llvm-svn: 117145
 2010-10-22 20:31:24 +00:00
Owen Anderson 9d0122af7d Add correct NEON encodings for vqdmlal. 
llvm-svn: 117134
 2010-10-22 19:35:48 +00:00
Jim Grosbach 2b80543fc2 Add the encoding information for the rest of the ARM mode multiply instructions. 
llvm-svn: 117133
 2010-10-22 19:15:30 +00:00
Owen Anderson 3d0264667f Provide correct encodings for NEON vmlal. 
llvm-svn: 117131
 2010-10-22 19:05:25 +00:00
Owen Anderson f48719f1b5 Provide correct NEON encodings for vmla. 
llvm-svn: 117126
 2010-10-22 18:54:37 +00:00
Stuart Hastings a8c4143bf6 Temporarily revert r117079; it broke a tester. Radar 6635085. 
llvm-svn: 117122
 2010-10-22 18:44:22 +00:00
Jim Grosbach 6956a60563 More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Owen Anderson f6659997a1 Add testscases for encoding of NEON vdqmull. 
llvm-svn: 117115
 2010-10-22 17:57:37 +00:00
Jim Grosbach 22261600a8 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
NAKAMURA Takumi c7e0dcf13f test/Makefile: Force lit -j1 on Cygwin. 
lit -jN causes crash on Cygwin's python.

llvm-svn: 117093
 2010-10-22 09:40:37 +00:00
Andrew Trick edd006c1c3 Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Sean Callanan 9f6c622f88 Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084
 2010-10-22 01:24:11 +00:00
Stuart Hastings cdc55bc680 Test case for r117075. Radar 6635085. 
llvm-svn: 117079
 2010-10-21 22:43:32 +00:00
Owen Anderson 28418de7ee Add tests for NEON encoding of vmull. 
llvm-svn: 117077
 2010-10-21 22:19:53 +00:00
Jim Grosbach a97becfaac ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Owen Anderson 22c940c9ab Add tests for NEON encoding of vqdmulh and vqrdmulh. 
llvm-svn: 117074
 2010-10-21 22:05:33 +00:00
Jim Grosbach 5edb03ee57 ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Owen Anderson eff79f13a6 Add tests for NEON vmul encoding. 
llvm-svn: 117069
 2010-10-21 21:51:58 +00:00
Owen Anderson 6e1cf114f9 Rename this test to better reflect its contents. 
llvm-svn: 117067
 2010-10-21 21:40:15 +00:00
Owen Anderson c47913acd2 Add tests for NEON encodings of vaddhn and vraddhn. 
llvm-svn: 117064
 2010-10-21 20:56:57 +00:00
Owen Anderson d8be664273 Add tests for NEON encodings of vqadd, which was already correctly encoded. 
llvm-svn: 117059
 2010-10-21 20:42:04 +00:00
Owen Anderson 6b7e401049 Add correct NEON encodings for vhadd and vrhadd. 
llvm-svn: 117047
 2010-10-21 18:55:04 +00:00
Owen Anderson 9561084188 Add correct encodings for NEON vaddw.s* and vaddw.u*. 
llvm-svn: 117040
 2010-10-21 18:20:25 +00:00
Owen Anderson 15c97706e8 Provide correct NEON encodings for vaddl.u* and vaddl.s*. 
llvm-svn: 117039
 2010-10-21 18:09:17 +00:00
Rafael Espindola 8ba86f801d Do not recurse into symbol refs that have a variant kind. This prevents us 
from losing the variant when producing a relocation on an alias.

llvm-svn: 117037
 2010-10-21 18:00:20 +00:00
Kevin Enderby 0138a05557 More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
 2010-10-21 17:16:46 +00:00
Bill Wendling 2a7d269a2b Fix whitespace. 
llvm-svn: 117002
 2010-10-21 06:25:08 +00:00
Wesley Peck c16f77fb27 Recommit 116986 with capitalization typo fixed. 
llvm-svn: 116993
 2010-10-21 03:57:26 +00:00
Andrew Trick f4ebec03e0 putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Wesley Peck 078db00f1d Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it 
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.

llvm-svn: 116991
 2010-10-21 03:34:22 +00:00
Owen Anderson 9e00f27e14 Revert r116983, which is breaking all the buildbots. 
llvm-svn: 116987
 2010-10-21 03:11:16 +00:00
Wesley Peck f608ac4db9 Major update of the MicroBlaze backend. The new features are: 
1. A delay slot filler that searches for valid instructions
       to fill the delay slot with. Previously NOPs would always
       be inserted into delay slots.
    2. Support for MC based instruction printer added.
    3. Support for MC based machine code generation and ELF
       file generation. ELF file generation does not yet
       completely work as much of the ELF support infrastructure
       is still x86/x86-64 specific.
    4. General clean up of the MBlaze backend code. Much of the
       tablegen code has been cleanup and simplified.

Bug Fixes:
    1. Removed duplicate periods from subtarget feature descriptions.
    2. Many of the instructions had bad machine code information
       in the tablegen files. Much of this has been fixed.

llvm-svn: 116986
 2010-10-21 03:09:55 +00:00
Evan Cheng 15c2ac90ec Add missing scheduling itineraries for transfers between core registers and VFP registers. 
llvm-svn: 116983
 2010-10-21 01:12:00 +00:00
Owen Anderson 6083502848 Implement correct encodings for NEON vadd, both integer and floating point. 
llvm-svn: 116981
 2010-10-21 00:48:00 +00:00
Bill Wendling a65f914bb0 Add encoding for moving a value between two ARM core registers and a doublework 
extension register.

llvm-svn: 116970
 2010-10-20 23:37:40 +00:00
Bill Wendling 058190507b Add encodings for movement between ARM core registers and single-precision 
registers.

llvm-svn: 116961
 2010-10-20 22:44:54 +00:00
Dan Gohman 55a028680c Add some comments. 
llvm-svn: 116957
 2010-10-20 22:04:02 +00:00
Evan Cheng 87066f0677 More accurate estimate / tracking of register pressure. 
- Initial register pressure in the loop should be all the live defs into the
  loop. Not just those from loop preheader which is often empty.
- When an instruction is hoisted, update register pressure from loop preheader
  to the original BB.
- Treat only use of a virtual register as kill since the code is still SSA.

llvm-svn: 116956
 2010-10-20 22:03:58 +00:00
Dale Johannesen ff37675c72 Fix crash introduced in 116852. 8573915. 
llvm-svn: 116955
 2010-10-20 22:03:37 +00:00
Jason W Kim ef3ba55e52 Cut unneeded global variable. 
llvm-svn: 116953
 2010-10-20 22:01:39 +00:00
Rafael Espindola 89f6613e76 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
llvm-svn: 116932
 2010-10-20 16:46:08 +00:00
Dale Johannesen 710a2d9d46 Enable using vdup for vector constants which are splat of 
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's.  8003375.

llvm-svn: 116852
 2010-10-19 20:00:17 +00:00
Evan Cheng 63c7608c34 Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
 2010-10-19 18:58:51 +00:00
Jason W Kim e8b3711ae9 Fixing r116753 r116756 r116777 
The failures in r116753 r116756 were caused by a python issue -
Python likes to append 'L' suffix to stringified numbers if the number
is larger than a machine int. Unfortunately, this causes a divergence of
behavior between 32 and 64 bit python versions.

I re-crafted elf-dump/common_dump to take care of these issues by:

1. always printing 0x (makes for easy sed/regex)
2. always print fixed length (exactly 2 + numBits/4 digits long)
   by mod ((2^numBits) - 1)
3. left-padded with '0'

There is a residual common routine that is also used by
macho-dump (dataToHex) , so I left the 'section_data' test values alone.

llvm-svn: 116823
 2010-10-19 17:39:10 +00:00
Daniel Dunbar 418204e523 Revert r116781 "- Add a hook for target to determine whether an instruction def 
is", which breaks some nightly tests.

llvm-svn: 116816
 2010-10-19 17:14:24 +00:00
Mikhail Glushenkov 2072db24ed GlobalOpt: EvaluateFunction() must not evaluate stores to weak_odr globals. 
Fixes PR8389.

llvm-svn: 116812
 2010-10-19 16:47:23 +00:00
Che-Liang Chiou 18d3e435cb Add test case mov.ll for PTX device function 
llvm-svn: 116806
 2010-10-19 13:21:51 +00:00
Rafael Espindola e73bc89093 Fix PR8300 by remembering to keep the bitcast in all cases. 
llvm-svn: 116788
 2010-10-19 02:02:57 +00:00
Evan Cheng 8249dfe6ce - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781
 2010-10-19 00:55:07 +00:00
Eric Christopher eac5e381cc Speculatively revert 116753 and 116756 to attempt to fix the bots. 
llvm-svn: 116777
 2010-10-19 00:19:49 +00:00
Bob Wilson b6d61dc291 Support alignment for NEON vld-lane and vst-lane instructions. 
llvm-svn: 116776
 2010-10-19 00:16:32 +00:00
Kevin Enderby 49843c0162 Added a few tweaks to the Intel Descriptor-table support instructions to allow 
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
 2010-10-19 00:01:44 +00:00
Eric Christopher 7b92c2a9a0 Revert r116220 - thus turning arm fast isel back on by default. 
llvm-svn: 116762
 2010-10-18 22:53:53 +00:00
Jason W Kim d4cc3d420a Get rid of unneeded FormatOutput global variable 
llvm-svn: 116756
 2010-10-18 21:59:38 +00:00
Jason W Kim eae048885d Changed elf-dump to output hex format by default. 
Also updated tests. 

llvm-svn: 116753
 2010-10-18 21:32:41 +00:00
Dan Gohman 408beac597 Don't pass the raw invalid pointer used to represent conflicting 
TBAA information to AliasAnalysis.

llvm-svn: 116751
 2010-10-18 21:28:00 +00:00
Dan Gohman fe8abf88a0 Add a basic testcase for TBAA-aware LICM. 
llvm-svn: 116745
 2010-10-18 21:00:09 +00:00
Rafael Espindola fba9f74932 Implement R_386_GOT32. 
llvm-svn: 116744
 2010-10-18 20:47:21 +00:00
Rafael Espindola 0a5314fdb3 Relocate with .bss instead of using the symbol. Matches gas behavior. 
llvm-svn: 116741
 2010-10-18 20:25:33 +00:00
Dan Gohman f7a5e20372 Run tbaa before basicaa, since that's how it's expected to be used. 
llvm-svn: 116731
 2010-10-18 18:45:59 +00:00
Rafael Espindola e3dc9e2ea1 Produce ELF::R_386_GOTPC relocations. 
llvm-svn: 116728
 2010-10-18 18:36:12 +00:00
Dan Gohman 33fcde9b9c Make TypeBasedAliasAnalysis default to doing nothing, with a command-line 
option to enable it.

llvm-svn: 116722
 2010-10-18 18:17:47 +00:00
Dan Gohman 02538ac4d3 Make BasicAliasAnalysis a normal AliasAnalysis implementation which 
does normal initialization and normal chaining. Change the default
AliasAnalysis implementation to NoAlias.

Update StandardCompileOpts.h and friends to explicitly request
BasicAliasAnalysis.

Update tests to explicitly request -basicaa.

llvm-svn: 116720
 2010-10-18 18:04:47 +00:00
Kevin Enderby b9783dd9bc Added a handful of x86-32 instructions that were missing so that llvm-mc would 
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716
 2010-10-18 17:04:36 +00:00
Rafael Espindola 3521f8467d Produce a R_386_PLT32 when needed. Moved the default cases of switches to the 
start for consistency.

llvm-svn: 116715
 2010-10-18 16:58:03 +00:00
Rafael Espindola 4464e0858f Handle GOTOFF correctly on i386. 
llvm-svn: 116711
 2010-10-18 16:38:04 +00:00
Kalle Raiskila 5f2034c455 Improve lowering of sext to i128 on SPU. 
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.

llvm-svn: 116701
 2010-10-18 09:34:19 +00:00
Rafael Espindola 4262a22225 Add a MCObjectFormat class so that code common to all targets that use a 
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

llvm-svn: 116675
 2010-10-16 18:23:53 +00:00
Benjamin Kramer 0d14b5b0fa Unbreak test on non-COFF targets. 
llvm-svn: 116669
 2010-10-16 11:27:13 +00:00
Michael J. Spencer 17990d5690 MC-COFF: Add support for default-null weak externals. 
llvm-svn: 116666
 2010-10-16 08:25:57 +00:00
Michael J. Spencer 5e683250ee X86-Windows: Emit an undefined global __fltused symbol when targeting Windows 
if any floating point arguments are passed to an external function.

llvm-svn: 116665
 2010-10-16 08:25:41 +00:00
Owen Anderson 18e4fed3fa Generalize MemCpyOpt's handling of call slot forwarding to function properly when the call slot 
forwarding is implemented with a load/store pair rather than a memcpy.

llvm-svn: 116637
 2010-10-15 22:52:12 +00:00
Mikhail Glushenkov 3ba051a4f6 llvmc: Add a test for the -c flag. 
llvm-svn: 116611
 2010-10-15 19:30:49 +00:00
Jim Grosbach 68a335e185 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Jakob Stoklund Olesen f28cc03802 FileCheckize 
llvm-svn: 116581
 2010-10-15 16:06:42 +00:00
Rafael Espindola fbcf0db7ee Refactor code a bit and avoid creating unnecessary entries in the string 
map.

llvm-svn: 116579
 2010-10-15 15:39:06 +00:00
Bob Wilson 59351844e1 ARM instructions that are both predicated and set the condition codes 
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!

llvm-svn: 116563
 2010-10-15 03:23:44 +00:00
Jim Grosbach 0b5c743811 Simplify test file a bit. 
llvm-svn: 116540
 2010-10-14 23:32:44 +00:00
Jim Grosbach 89efff3763 Add testcase for RRX and ASRS (which effectively tests MOVs, since those 
are just forms of that instruction).

llvm-svn: 116538
 2010-10-14 23:29:18 +00:00
Jim Grosbach 8b6a9c1574 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534
 2010-10-14 22:57:13 +00:00
Jim Grosbach 062749cb25 Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

llvm-svn: 116512
 2010-10-14 20:43:44 +00:00
Jim Grosbach eafcb27ded MOVi16 and MOVT ARM mode encodings. 
llvm-svn: 116498
 2010-10-14 18:54:27 +00:00
Rafael Espindola bee6e9f8e0 Remove some code duplication. 
llvm-svn: 116484
 2010-10-14 16:34:44 +00:00
Mikhail Glushenkov 793d141b7d Comments. 
llvm-svn: 116476
 2010-10-14 13:43:20 +00:00
Bill Wendling 6f52f8a87d Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on 
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471
 2010-10-14 02:33:26 +00:00
Bill Wendling 0441c6cba0 Add encoding for 'fmstat'. 
llvm-svn: 116466
 2010-10-14 01:19:34 +00:00
Bill Wendling 0825f3e441 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464
 2010-10-14 01:02:08 +00:00
Chris Lattner b9681ad442 fix a bug I introduced, no idea how this didn't repro right. 
llvm-svn: 116462
 2010-10-14 00:30:00 +00:00
Chris Lattner c7bd5740eb hack to unbreak buildbots 
llvm-svn: 116461
 2010-10-14 00:26:10 +00:00
Chris Lattner 698661c741 add uadd_ov/usub_ov to apint, consolidate constant folding 
logic to use the new APInt methods.  Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold

which comes from "clang -ftrapv", originally brought to my attention from PR8221.

llvm-svn: 116457
 2010-10-14 00:05:07 +00:00
Jim Grosbach 7e72ec6626 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
 2010-10-13 21:00:04 +00:00
Bill Wendling f106ecfa59 Add MC encodings for VCVT* instrunctions. 
llvm-svn: 116431
 2010-10-13 20:58:46 +00:00
Jim Grosbach 1e7db68774 Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach 651dc7c9e9 Add ARM mode operand encoding information for ADDE/SUBE instructions. 
llvm-svn: 116412
 2010-10-13 18:00:52 +00:00